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PDF 8T74S208C-01 Data sheet ( Hoja de datos )
| Número de pieza | 8T74S208C-01 | |
| Descripción | 2.5 V Differential LVDS Clock Divider and Fanout Buffer | |
| Fabricantes | IDT | |
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2.5 V Differential LVDS Clock Divider
and Fanout Buffer
8T74S208C-01
Datasheet
General Description
The 8T74S208C-01 is a high-performance differential LVDS clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T74S208C-01 is characterized to operate from a 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T74S208C-01 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I2C register. On
power-up, all outputs are disabled.
Features
One differential input reference clock
Differential pair can accept the following differential input levels:
LVDS, LVPECL, CML
Integrated input termination resistors
Eight LVDS outputs
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum input clock frequency: 1GHz
LVCMOS interface levels for the control inputs
Individual output enabled/ disabled by I2C interface
Output skew: 45ps (maximum)
Output rise/fall times: 370ps (maximum)
Low additive phase jitter, RMS: 96fs (typical)
Full 2.5V supply voltage
Outputs disabled at power-up
Lead-free (RoHS 6) 32-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
IN
nIN
50
fREF
÷1, ÷2,
÷4, ÷8
50
VT
FSEL[1:0] Pulldown (2)
2
SDA Pullup
SCL Pullup
ADR[1:0] Pulldown (2)
2
I2C
8
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
ADR1
GND
Q0
nQ0
Q1
nQ1
GND
VDDO
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
8T74S208A
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
FSEL0
GND
nQ7
Q7
nQ6
Q6
GND
VDDO
Q7 8T74S208C-01
nQ7
32-Lead VFQFN, 5mm x 5mm x 0.925mm
©2016 Integrated Device Technology, Inc.
1
August 22, 2016
1 page  
8T74S208C-01 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Electrical Characteristics
or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Item
Supply Voltage, VDD
Inputs, VI
Input Termination Current, IVT
Outputs, IO
Continuous Current
Surge Current
Storage Temperature, TSTG
Maximum Junction Temperature, TJMAX
ESD - Human Body Model 1
ESD - Charged Device Model 1
NOTE 1: According to JEDEC/JS-001-2012/JESD22-C101E.
Rating
4.6V
-0.5V to VDD + 0.5V
±35mA
10mA
15mA
-65C to 150C
125°C
2000V
500V
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VDD
VDDO
IDD
IDDO
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
All Outputs are Enabled and
Terminated
2.375
2.375
2.5
2.5
54
155
.
Table 4B. LVCMOS/LVTTL Input DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
FSEL[1:0],
VIH
Input
High Voltage1
ADR[1:0]
SCL, SDA
VDD = 2.5V ± 5%
VDD = 2.5V ± 5%
1.7
1.9
FSEL[1:0],
VIL
Input
Low Voltage1
ADR[1:0]
SCL, SDA
VDD = 2.5V ± 5%
VDD = 2.5V ± 5%
-0.3
-0.3
FSEL[1:0],
IIH
Input
High Current
ADR[1:0]
SCL, SDA
VDD = VIN = 2.625V
VDD = VIN = 2.625V
FSEL[1:0],
IIL
Input
Low Current
ADR[1:0]
SCL, SDA
VDD = 2.625V, VIN = 0V
VDD = 2.625V, VIN = 0V
-10
-150
NOTE 1: VIL should not be lower than -0.3V and VIH should not be higher than VDD + 0.3V.
Maximum
2.625
2.625
64
182
Maximum
VDD + 0.3
VDD + 0.3
0.7
0.5
150
5
Units
V
V
mA
mA
Units
V
V
V
V
µA
µA
µA
µA
©2016 Integrated Device Technology, Inc.
5
August 22, 2016
5 Page 
8T74S208C-01 Datasheet
Applications Information
Differential Input with Built-In 50 Termination Interface
The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,
CML and other differential signals. Both differential signals must
meet the VIN and VCMR requirements. Figure 4A to Figure 4C show
interface examples for the IN/nIN input with built-in 50 terminations
driven by the most common driver types. The input interfaces
suggested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termination
requirements.
3.3V or 2.5V
LVDS
2.5V
Zo = 50Ω
Zo = 50Ω
IN
50Ω
VT
50Ω
nIN
Receiver
w ith Built-in
50Ω
Figure 4A. IN/nIN Input with Built-In 50 driven by an
LVDS Driver
2.5V
LVPECL
Zo = 50Ω
Zo = 50Ω
R1
18Ω
2.5V
IN
50Ω
VT
50Ω
nIN
Receiver
w ith Built-in
50Ω
Figure 4C. IN/nIN Input with Built-In 50 driven by an
LVPECL Driver
2.5V
Zo = 50Ω
Zo = 50Ω
CML – Open Collector
2.5V
IN
50Ω
VT
50Ω
nIN
Receiver
with Built-in
50Ω
Figure 4B. IN/nIN Input with Built-In 50 Driven by a CML
Driver with Open Collector
©2016 Integrated Device Technology, Inc.
11
August 22, 2016
11 Page | ||
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