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PDF AD2S80A Data sheet ( Hoja de datos )
| Número de pieza | AD2S80A | |
| Descripción | Monolithic Resolver-to-Digital Converter | |
| Fabricantes | Analog Devices | |
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a
Variable Resolution, Monolithic
Resolver-to-Digital Converter
AD2S80A
FEATURES
Monolithic (BiMOS ll) Tracking R/D Converter
40-Lead DIP Package
44-Terminal LCC Package
10-,12-,14-, and 16-Bit Resolution Set by User
Ratiometric Conversion
Low Power Consumption: 300 mW Typ
Dynamic Performance Set by User
High Max Tracking Rate 1040 RPS (10 Bits)
Velocity Output
Industrial Temperature Range Versions
Military Temperature Range Versions
ESD Class 2 Protection (2,000 V Min)
/883 B Parts Available
APPLICATIONS
DC Brushless and AC Motor Control
Process Control
Numerical Control of Machine Tools
Robotics
Axis Control
Military Servo Control
GENERAL DESCRIPTION
The AD2S80A is a monolithic 10-, 12-, 14-, or 16-bit tracking
resolver-to-digital converter contained in a 40-lead DIP or 44-
terminal LCC ceramic package. It is manufactured on a BiMOS
II process that combines the advantages of CMOS logic and
bipolar high accuracy linear circuits on the same chip.
The converter allows users to select their own resolution and dynamic
performance with external components. This allows the users great
flexibility in defining the converter that best suits their system
requirements. The converter allows users to select the resolution
to be 10, 12, 14, or 16 bits and to track resolver signals rotating
at up to 1040 revs per second (62,400 rpm) when set to 10-bit
resolution.
The AD2S80A converts resolver format input signals into a
parallel natural binary digital word using a ratiometric tracking
conversion method. This ensures high-noise immunity and toler-
ance of lead length when the converter is remote from the resolver.
The 10-, 12-, 14- or 16-bit output word is in a three-state digital
logic available in 2 bytes on the 16 output data lines. BYTE
SELECT, ENABLE and INHIBIT pins ensure easy data trans-
fer to 8- and 16-bit data buses, and outputs are provided to
allow for cycle or pitch counting in external counters.
An analog signal proportional to velocity is also available and
can be used to replace a tachogenerator.
The AD2S80A operates over 50 Hz to 20,000 Hz reference
frequency.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
SIN I/P
SIG GND
COS I/P
ANALOG
GND
RIPPLE
CLK
DATA
LOAD
+12V
–12V
AD2S80A
A1 A3
SEGMENT
SWITCHING
A2
R-2R
DAC
PHASE
SENSITIVE
DETECTOR
16-BIT UP/DOWN COUNTER
VCO DATA
TRANSFER
LOGIC
OUTPUT DATA LATCH
INTEGRATOR
O/P
VCO I/P
16 DATA BITS
PRODUCT HIGHLIGHTS
Monolithic. A one chip solution reduces the package size
required and increases the reliability.
Resolution Set by User. Two control pins are used to select
the resolution of the AD2S80A to be 10, 12, 14, or 16 bits allowing
the user to use the AD2S80A with the optimum resolution for
each application.
Ratiometric Tracking Conversion. Conversion technique
provides continuous output position data without conversion
delay and is insensitive to absolute signal levels. It also provides
good noise immunity and tolerance to harmonic distortion on
the reference and input signals.
Dynamic Performance Set by the User. By selecting exter-
nal resistor and capacitor values the user can determine bandwidth,
maximum tracking rate and velocity scaling of the converter to
match the system requirements. The external components
required are all low cost preferred value resistors and capacitors,
and the component values are easy to select using the simple
instructions given.
Velocity Output. An analog signal proportional to velocity is
available and is linear to typically one percent. This can be used
in place of a velocity transducer in many applications to provide
loop stabilization in servo controls and velocity feedback data.
Low Power Consumption. Typically only 300 mW.
Military Product. The AD2S80A is available processed in
accordance with MIL-STD-883B, Class B.
MODELS AVAILABLE
Information on the models available is given in the section
“Ordering Information.”
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
©Analog Devices, Inc., 1986–2015
1 page  
AD2S80A–SPECIFICATIONS (typical at 25؇C unless otherwise noted)
Parameter
Conditions
Min Typ Max
RATIO MULTIPLIER
AC Error Output Scaling
10 Bit
12 Bit
14 Bit
16 Bit
177.6
44.4
11.1
2.775
PHASE SENSITIVE DETECTOR
Output Offset Voltage
Gain
In Phase
In Quadrature
Input Bias Current
Input Impedance
Input Voltage
w.r.t. REF
w.r.t. REF
–0.882
1
12
–0.9 –0.918
± 0.02
60 150
±8
INTEGRATOR
Open-Loop Gain
Dead Zone Current (Hysteresis)
Input Offset Voltage
Input Bias Current
Output Voltage Range
VCO
Maximum Rate
VCO Rate
VCO Power Supply Sensitivity
Increase
Decrease
Input Offset Voltage
Input Bias Current
Input Bias Current Tempco
Input Voltage Range
Linearity of Absolute Rate
Full Range
Over 0% to 50% of Full Range
Reversion Error
Sensitivity of Reversion Error
to Symmetry of Power Supplies
At 10 kHz
± VS = ± 10.8 V dc
± VS = ± 12 V dc
Positive Direction
Negative Direction
+VS
–VS
+VS
–VS
57 63
100
15
60 150
±7
1.1
7.1 7.9 8.7
7.1 7.9 8.7
+0.5
–8.0
–8.0
+2.0
1
70
–1.22
5
380
±8
<2
<1
1.5
±8
POWER SUPPLIES
Voltage Levels
+VS
–VS
+VL
Current
± IS
± IS
± IL
± VS @ ± 12 V
± VS @ 13.2 V
+VL @ ± 5.0 V
+10.8
–10.8
+5
؎12
؎19
؎0.5
+13.2
–13.2
+13.2
؎23
؎30
؎1.5
Specification subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
Unit
mV/Bit
mV/Bit
mV/Bit
mV/Bit
mV
V rms/V dc
V rms/V dc
nA
MΩ
V
dB
nA/LSB
mV
nA
V
MHz
kHz/µA
kHz/µA
%/V
%/V
%/V
%/V
mV
nA
nA/°C
V
% FSD
% FSD
% FSD
%/V of
Asymmetry
V
V
V
mA
mA
mA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD2S80A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4– REV. D
5 Page 
AD2S80A
CIRCUIT FUNCTIONS AND DYNAMIC PERFORMANCE
The AD2S80A allows the user greater flexibility in choosing the
dynamic characteristics of the resolver-to-digital conversion to
ensure the optimum system performance. The characteristics
are set by the external components shown in Figure 1, and the
section “COMPONENT SELECTION” explains how to select
desired maximum tracking rate and bandwidth values. The
following paragraphs explain in greater detail the circuit of the
AD2S80A and the variations in the dynamic performance avail-
able to the user.
Loop Compensation
The AD2S80A (connected as shown in Figure 1) operates as a
Type 2 tracking servo loop where the VCO/counter combination
and Integrator perform the two integration functions inherent in
a Type 2 loop.
Additional compensation in the form of a pole/zero pair is
required to stabilize any Type 2 loop to avoid the loop gain
characteristic crossing the 0 dB axis with 180° of additional
phase lag, as shown in Figure 5.
This compensation is implemented by the integrator compo-
nents (R4, C4, R5, C5).
The overall response of such a system is that of a unity gain
second order low pass filter, with the angle of the resolver as the
input and the digital position data as the output.
The AD2S80A does not have to be connected as tracking con-
verter, parts of the circuit can be used independently. This is
particularly true of the Ratio Multiplier which can be used as a
control transformer (see Application Note).
A block diagram of the AD2S80A is given in Figure 3.
AC ERROR
R5 C5
C4
sin sin t
cos sin t
RATIO
MULTIPLIER
DIGITAL
A1 sin ( – ) sin t
CLOCK
DIRECTION
PHASE
SENSITIVE
DEMODULATOR
VCO
Figure 3. Functional Diagram
R4
INTEGRATOR
R6
VELOCITY
Ratio Multiplier
The ratio multiplier is the input section of the AD2S80A and
compares the signal from the resolver input angle, θ, to the
digital angle, φ, held in the counter. Any difference between
these two angles results in an analog voltage at the AC ERROR
OUTPUT. This circuit function has historically been called
a “Control Transformer” as it was originally performed by an
electromechanical device known by that name.
The AC ERROR signal is given by
A1 sin (θ–φ) sin ωt
where ω = 2 π fREF
fREF = reference frequency
A1, the gain of the ratio multiplier stage is 14.5.
So for 2 V rms inputs signals
AC ERROR output in volts/(bit of error)
=
2
×
sin
360
n
×
A1
where n = bits per rev
= 1,024 for 10 bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits
giving an AC ERROR output
= 178 mV/bit @ 10 bits resolution
= 44.5 mV/bit @ 12 bits
= 11.125 mV/bit @ 14 bits
= 2.78 mV/bit @ 16 bits
The ratio multiplier will work in exactly the same way whether
the AD2S80A is connected as a tracking converter or as a con-
trol transformer, where data is preset into the counters using the
DATA LOAD pin.
HF Filter
The AC ERROR OUTPUT may be fed to the PSD via a simple
ac coupling network (R2, C1) to remove any dc offset at this
point. Note, however, that the PSD of the AD2S80A is a wide-
band demodulator and is capable of aliasing HF noise down to
within the loop bandwidth. This is most likely to happen where
the resolver is situated in particularly noisy environments, and
the user is advised to fit a simple HF filter R1, C2 prior to the
phase sensitive demodulator.
The attenuation and frequency response of a filter will affect the
loop gain and must be taken into account in deriving the loop
transfer function. The suggested filter (R1, C1, R2, C2) is
shown in Figure 1 and gives an attenuation at the reference
frequency (fREF) of 3 times at the input to the phase sensitive
demodulator .
Values of components used in the filter must be chosen to ensure
that the phase shift at fREF is within the allowable signal to
reference phase shift of the converter.
Phase Sensitive Demodulator
The phase sensitive demodulator is effectively ideal and devel-
ops a mean dc output at the DEMODULATOR OUTPUT
pin of
±2
π
2
× (DEMODULATOR
INPUT rms voltage )
–10–
REV. D
11 Page | ||
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| PDF Descargar | [ Datasheet AD2S80A.PDF ] | |
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