EiceDRIVER™ Compact
High voltage gate driver IC
2EDL family
600 V half bridge gate drive IC
2EDL23I06PJ
2EDL23N06PJ
EiceDRIVER™ Compact
Final datasheet
<Revision 2.2>, 01.06.2016
Final
Industrial Power Control
No Preview Available !

1 page



EiceDRIVER™ Compact
2EDL family
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Typical Application ...............................................................................................................................8
Block diagram for 2EDL23x06PJ .........................................................................................................9
Pin Configuration of 2EDL family .......................................................................................................10
Input pin structure...............................................................................................................................11
Input filter timing diagram ...................................................................................................................11
EN-/FLT pin structures and interface to microcontroller (µC) ............................................................12
Timing of short pulse suppression .....................................................................................................19
Timing of of internal deadtime............................................................................................................19
Enable delay time definition ...............................................................................................................19
Input to output propagation delay times and switching times definition .............................................20
Operating areas (IGBT UVLO levels).................................................................................................20
Operating areas (MOSFET UVLO levels) ..........................................................................................20
ITRIP-Timing ......................................................................................................................................21
Output pulse width timing and matching delay timing diagram for positive logic...............................21
Package drawing................................................................................................................................22
PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint....22
Final datasheet
5 <Revision 2.2>, 01.06.2016

5 Page