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What is MC10H351?

This electronic component, produced by the manufacturer "Motorola Semiconductors", performs the same function as "Quad TTL/NMOS to PECL Translator".


MC10H351 Datasheet PDF - Motorola Semiconductors

Part Number MC10H351
Description Quad TTL/NMOS to PECL Translator
Manufacturers Motorola Semiconductors 
Logo Motorola Semiconductors Logo 


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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad TTL/NMOS to PECL*
Translator
MC10H351
The MC10H351 is a quad translator for interfacing data between a
saturated logic section and the PECL section of digital systems when only
a +5.0 Vdc power supply is available. The MC10H351 has TTL/NMOS
compatible inputs and PECL complementary open–emitter outputs that
allow use as an inverting/non–inverting translator or as a differential line
driver. When the common strobe input is at a low logic level, it forces all
true outputs to the PECL low logic state (+3.2 V) and all inverting
outputs to the PECL high logic state (+4.1 V).
The MC10H351 can also be used with the MC10H350 to transmit and
receive TTL/NMOS information differentially via balanced twisted pair
lines.
Single +5.0 Power Supply
All VCC Pins Isolated On Chip
Differentially Drive Balanced Lines
tpd = 1.3 nsec Typical
MAXIMUM RATINGS
Characteristic
Power Supply
Input Voltage (VCC = 5.0 V)
Output Current — Continuous
— Surge
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
Symbol
VCC
VI
Iout
TA
Tstg
Rating
0 to +7.0
0 to VCC
50
100
0 to +75
–55 to +150
–55 to +165
Unit
Vdc
Vdc
mA
°C
°C
ELECTRICAL CHARACTERISTICS (VCC = VCC1 = VCC2 = 5.0 V ± 5.0%)
0° 25° 75°
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply
Current
ECL — 50 — 45 — 50 mA
TTL — 20 — 15 — 20 mA
Reverse Current
Pins 7, 8, 12, 14
Pin 9
IR
IINH
— 25 —
— 100 —
20 —
80 —
µA
25
100
Forward Current
Pins 7, 8, 12, 14
Pin 9
mA
IF — –0.8 — –0.6 — –0.8
IINL — –3.2 — –2.4 — –3.2
Input Breakdown
Voltage
V(BR)in 5.5 — 5.5 — 5.5
— Vdc
Input Clamp Voltage
(Iin = –18 mA)
High Output
Voltage (1)
VI — –1.5 — –1.5 — –1.5 Vdc
VOH 3.98 4.16 4.02 4.19 4.08 4.27 Vdc
Low Output
Voltage (1)
VOL 3.05 3.37 3.05 3.37 3.05 3.37 Vdc
High Input Voltage
Low Input Voltage
VIH 2.0 — 2.0 — 2.0 — Vdc
VIL
— 0.8 — 0.8 —
0.8 Vdc
(1) With VCC at 5.0 V. VOH/VOL change 1:1 with VCC.
*Positive Emitter Coupled Logic
L SUFFIX
CERAMIC PACKAGE
CASE 732–03
P SUFFIX
PLASTIC PACKAGE
CASE 738–03
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
B IN 7
A IN 8
D IN 12
C IN 14
COMMON 9
STROBE
1 B OUT
2 B OUT
5 A OUT
4 A OUT
16 D OUT
17 D OUT
19 C OUT
18 C OUT
VCC (+5.0 VDC) = PINS 6, 11, 15, 20
GND = PIN 10
DIP
PIN ASSIGNMENT
B OUT
B OUT
1
2
20 ECL VCC
19 C OUT
N.C. 3
18 C OUT
A OUT
4
17 D OUT
A OUT
5
16 D OUT
VCC 6
B IN 7
15 VCC 2
14 C IN
A IN 8
13 N.C.
COMMON
STROBE
9
12 D IN
GND 10
11 TTL VCC
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–36 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
2–77
REV 5


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