TDA21211 Datasheet PDF

TDA21211 - Infineon

Part Number TDA21211
Description High-Performance DrMOS
Manufacturers Infineon 
Logo Infineon Logo 
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TDA21211 datasheet
TDA21211 pdf, equivalent, schematic
6x6 QFN High-Performance DrMOS
Intel compliant DrMOS, Power MOSFET and
Driver in one package
For Synchronous Buck - step down voltage
Maximum Average Current of 35A
Wide input voltage range +5V to +30V
Low power dissipation
Extremely fast switching technology for
improved performance at high switching
frequencies (>1MHz)
Remote Driver Disable function
Switching Modulation (SMOD#) of low side
Includes active PMOS structure as integrated
bootstrap circuit for reduced part count
Shoot through protection
+5V High and Low Side Driving voltage
Compatible to standard PWM controller ICs with
+3.3 and 5V logic
Three-State PWM input functionality
Small Package: IQFN40 (6 x 6 x 0.8 mm3)
RoHS Compliant
Desktop and Server
VR11.X and VR12 Vcore
and non-Vcore buck-
Network and Telecom
processor VR
Single Phase and Multi-
Phase POL
CPU/GPU Regulation in
Notebook, Graphics Cards,
and Gaming
Voltage Modules requiring
high power density
Memory (DDR2/3)
Data Sheet
Page 2 of 20
TDA21211 transistor, diode fet, igbt, scr
Inputs to the internal control circuit are PWM, DISB# and SMOD#:
The PWM is the control input to the IC from an external PWM controller and is compatible with 3.3V and 5V logic.
The PWM input has three-state functionality. When the voltage remains in the specified PWM-shutdown-window for at
least the PWM-shutdown-holdoff time T_tsshd, the operation will be suspended by keeping both MOSFET gate outputs
low. Once left open, the pin is internally fixed to VPWM_O = 1.5 V level
Driver Output
GL=H, GH = L
GL=L, GH = H
GL=L, GH = L
The DISB# is an active low signal. When DISB# is pulled low, the power stage is disabled.
Driver Output
Shutdown Æ GL, GH = L
EnableÆ GL, GH = “Active”
Shutdown Æ GL, GH = L
The SMOD# feature is provided to disable the low-side MOSFET during active operation. When synchronized with the
PWM signal (as shown in Figure 7), SMOD# is intended to improve light load efficiency by saving the gate charge loss
of the low-side MOSFET. Once left open, the pin is internally fixed to VSMOD#_O = 3 V level.
GL Status
Enable Æ GL= “Active”
Enable Æ GL= “Active”
The TDA21211 driver includes gate drive functionality to protect against shoot through. In order to protect the power
stage from overlap, both HS and LS MOSFETs being on at the same time, the adaptive control circuitry monitors the
voltage at the “VSWH” pin. When the PWM signal goes low, HS, the High-side MOSFET will begin to turn off, after the
propagation delay (T_pdlu). Once the “VSWH” pin falls below 1V, LS, the Low-side MOSFET is gated on after the
predefined delay time, (T_pdhl). Additionally, the gate to source voltage of the HS-MOSFET is also monitored. When
VGS(HS) is discharged below 1V, a threshold known to turn HS off, a secondary delay is initiated, (T_pdhl), which
results in LS being gated “ON” irregardless of the state of the “VSWH” pin.This way it will be ensured that the converter
can sink current efficiently and the bootstrap capacitor will be refreshed appropriately during each switching cycle. See
Figure 5 for more detail.
GH and GL are monitoring pins to check the internal gate drive signals.
Data Sheet
Page 9 of 20

Information Total 20 Pages
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