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PDF CY7C12771KV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C12771KV18 | |
| Descripción | 1.8 V synchronous pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C12661KV18, CY7C12771KV18
CY7C12681KV18, CY7C12701KV18
36-Mbit DDR II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency)
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■ 36-Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)
■ 550 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces
(data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ DDR II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR I device with 1 Cycle Read Latency
when DOFF is asserted LOW
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1]
❐ Supports both 1.5 V and 1.8 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C12661KV18 – 4 M × 8
CY7C12771KV18 – 4 M × 9
CY7C12681KV18 – 2 M × 18
CY7C12701KV18 – 1 M × 36
Functional Description
The CY7C12661KV18, CY7C12771KV18, CY7C12681KV18,
and CY7C12701KV18 are 1.8 V synchronous pipelined SRAMs
equipped with DDR II+ architecture. The DDR II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 8-bit
words (CY7C12661KV18), 9-bit words (CY7C12771KV18),
18-bit words (CY7C12681KV18), or 36-bit words
(CY7C12701KV18) that burst sequentially into or out of the
device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
These devices are down bonded from the 65 nm 72 M
QDRII+/DDRII+ devices and hence have the same IDD/ISB1
values and the same JTAG ID code as the equivalent 72 M
device options. For details refer to the application note AN53189,
65 nm Technology InterimQDRII+/DDRII+ SRAM device family
description.
Table 1. Selection Guide
Description
550
MHz
Max operating frequency
550
Max operating current × 8 740
× 9 740
× 18 760
× 36 970
500
MHz
500
690
690
700
890
450
MHz
450
630
630
650
820
400
MHz
400
580
580
590
750
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-53195 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 2, 2011
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CY7C12661KV18, CY7C12771KV18
CY7C12681KV18, CY7C12701KV18
Pin Configuration
The pin configuration for CY7C12661KV18, CY7C12771KV18, CY7C12681KV18, and CY7C12701KV18 follow. [2]
165-ball FBGA (13 × 15 × 1.4 mm) Pinout
CY7C12661KV18 (4 M × 8)
1 2 3 4 5 6 7 8 9 10
A
CQ NC/72M
A
R/W
NWS1
K NC/144M LD
A
A
B
NC NC NC
A NC/288M K
NWS0
A
NC NC
C NC NC NC VSS A A A VSS NC NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
E
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
G
NC
NC
DQ5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J
NC
NC
NC VDDQ VDD
VSS
VDD
VDDQ
NC
DQ1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
L
NC
DQ6
NC VDDQ VSS
VSS
VSS
VDDQ
NC
NC
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
N NC NC NC VSS A A A VSS NC NC
P NC NC DQ7 A
A QVLD A
A NC NC
R
TDO
TCK
A
A
A NC A
A
A TMS
CY7C12771KV18 (4 M × 9)
1 2 3 4 5 6 7 8 9 10
A
CQ NC/72M
A
R/W NC
K NC/144M LD
A
A
B
NC NC NC
A NC/288M K
BWS0
A
NC NC
C NC NC NC VSS A A A VSS NC NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
E
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
G
NC
NC
DQ5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J
NC
NC
NC VDDQ VDD
VSS
VDD
VDDQ
NC
DQ1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
L
NC
DQ6
NC VDDQ VSS
VSS
VSS
VDDQ
NC
NC
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
N NC NC NC VSS A A A VSS NC NC
P NC NC DQ7 A
A QVLD A
A NC NC
R
TDO
TCK
A
A
A NC A
A
A TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
DQ8
TDI
Note
2. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-53195 Rev. *E
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CY7C12661KV18, CY7C12771KV18
CY7C12681KV18, CY7C12701KV18
The truth table for the CY7C12661KV18, CY7C12771KV18, CY7C12681KV18, and CY7C12701KV18 follow. [3, 4, 5, 6, 7, 8]
Table 3. Truth Table
Operation
K LD R/W
DQ
DQ
Write cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
L-H
L
L D(A) at K(t + 1) D(A+1) at K(t + 1)
Read cycle: (2.5 cycle latency)
Load address; wait two and half cycles;
read data on consecutive K and K rising edges.
L-H L
H Q(A) at K(t + 2) Q(A+1) at K(t + 3)
NOP: No operation
L-H H
X High Z
High Z
Standby: Clock stopped
Stopped
X
X Previous state
Previous state
The write cycle description table for CY7C12661KV18 and CY7C12681KV18 follows. [3, 9]
Table 4. Write Cycle Descriptions
BWS0/ BWS1/
NWS0 NWS1
K
K
Comments
L L L–H – During the data portion of a write sequence
CY7C12661KV18 both nibbles (D[7:0]) are written into the device.
CY7C12681KV18 both bytes (D[17:0]) are written into the device.
L L – L-H During the data portion of a write sequence
CY7C12661KV18 both nibbles (D[7:0]) are written into the device.
CY7C12681KV18 both bytes (D[17:0]) are written into the device.
L H L–H – During the data portion of a write sequence
CY7C12661KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C12681KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L H – L–H During the data portion of a write sequence
CY7C12661KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C12681KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H L L–H – During the data portion of a write sequence
CY7C12661KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C12681KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H L – L–H During the data portion of a write sequence
CY7C12661KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C12681KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
Notes
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
4. Device powers up deselected with the outputs in a tristate condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
8. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9.
Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table.
different portions of a write cycle, as long as the setup and hold requirements are achieved.
NWS0,
NWS1,
BWS0,
BWS1,
BWS2,
and
BWS3
can
be
altered
on
Document Number: 001-53195 Rev. *E
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C12771KV18.PDF ] | |
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