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S25FL512S Datasheet PDF - Cypress Semiconductor

Part Number S25FL512S
Description 512 Mbit (64 Mbyte) 3.0V SPI Flash Memory
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 

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S25FL512S datasheet, circuit
S25FL512S
512 Mbit (64 Mbyte)
3.0V SPI Flash Memory
Features
CMOS 3.0 Volt Core with Versatile I/O
Serial Peripheral Interface with Multi-I/O
Density
– 512 Mbits (64 Mbytes)
Serial Peripheral Interface (SPI)
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 32-bit address
– Serial Command set and footprint compatible with S25FL-A,
S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
– AutoBoot - power up or reset and execute a Normal or Quad read
command automatically at a preselected address
– Common Flash Interface (CFI) data for configuration information.
Programming (1.5 Mbytes/s)
– 512-byte Page Programming buffer
– Quad-Input Page Programming (QPP) for slow clock systems
– Automatic ECC -internal hardware Error Correction Code
generation with single bit error correction
Erase (0.5 to 0.65 Mbytes/s)
– Uniform 256-kbyte sectors
Cycling Endurance
– 100,000 Program-Erase Cycles
Data Retention
– 20 Year Data Retention
Security features
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against program or erase
of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or password
Cypress® 65 nm MirrorBit® Technology with EclipseArchitecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
– SO16 and FBGA packages
Temperature Range:
– Industrial (-40°C to +85°C)
– Industrial Plus (-40°C to +105°C)
– Extended (-40°C to +125°C)
– Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)
– Automotive, AEC-Q100 Grade 2 (–40°C to +105°C)
– Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)
Packages (all Pb-free)
– 16-lead SOIC (300 mil)
– BGA-24 6 x 8 mm
– 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint options
– Known Good Die and Known Tested Die
Logic Block Diagram
CS#
SCK
SI/IO0
SO/IO1
WP#/IO2
HOLD#/IO3
RESET#
I/O
SRAM
Control
Logic
MirrorBit Array
Y Decoders
Data Latch
Data Path
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-98284 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 20, 2016

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S25FL512S equivalent
S25FL512S
1.2 Migration Notes
1.2.1
Features Comparison
The S25FL512S device is command set and footprint compatible with prior generation FL-K and FL-P families.
Table 1.1 FL Generations Comparison
Parameter
Technology Node
Architecture
Release Date
Density
Bus Width
Supply Voltage
Normal Read Speed (SDR)
Fast Read Speed (SDR)
Dual Read Speed (SDR)
Quad Read Speed (SDR)
Fast Read Speed (DDR)
Dual Read Speed (DDR)
Quad Read Speed (DDR)
Program Buffer Size
Erase Sector Size
Parameter Sector Size
Sector Erase Time (typ.)
Page Programming Time (typ.)
OTP
Advanced Sector Protection
Auto Boot Mode
Erase Suspend/Resume
Program Suspend/Resume
Operating Temperature
FL-K
90 nm
Floating Gate
In Production
4 Mb - 128 Mb
x1, x2, x4
2.7V - 3.6V
6 MB/s (50 MHz)
13 MB/s (104 MHz)
26 MB/s (104 MHz)
52 MB/s (104 MHz)
256B
4 kB / 32 kB / 64 kB
4 kB
30 ms (4 kB), 150 ms (64 kB)
700 µs (256B)
768B (3 x 256B)
No
No
Yes
Yes
–40°C to +85°C
Notes:
1. 256B program page option only for 128-Mb and 256-Mb density FL-S devices.
2. FL-P column indicates FL129P MIO SPI device (for 128-Mb density).
3. 64 kB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.
4. FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.
5. Refer to individual data sheets for further details.
FL-P
90 nm
MirrorBit
In Production
32 Mb - 256 Mb
x1, x2, x4
2.7V - 3.6V
5 MB/s (40 MHz)
13 MB/s (104 MHz)
20 MB/s (80 MHz)
40 MB/s (80 MHz)
256B
64 kB / 256 kB
4 kB
500 ms (64 kB)
1500 µs (256B)
506B
No
No
No
No
–40°C to +85°C / +105°C
FL-S
65 nm
MirrorBit Eclipse
In Production
512 Mb
x1, x2, x4
2.7V - 3.6V / 1.65V - 3.6V VIO
6 MB/s (50 MHz)
17 MB/s (133 MHz)
26 MB/s (104 MHz)
52 MB/s (104 MHz)
20 MB/s (80 MHz)
40 MB/s (80 MHz)
80 MB/s (80 MHz)
512B
256 kB
520 ms (256 kB)
340 µs (512B)
1024B
Yes
Yes
Yes
Yes
–40°C to +85°C / +105°C
1.2.2
Known Differences from Prior Generations
1.2.2.1
Error Reporting
Prior generation FL memories either do not have error status bits or do not set them if program or erase is attempted on a protected
sector. The FL-S family does have error reporting status bits for program and erase operations. These can be set when there is an
internal failure to program or erase or when there is an attempt to program or erase a protected sector. In either case the program or
erase operation did not complete as requested by the command.
1.2.2.2
Secure Silicon Region (OTP)
The size and format (address map) of the One Time Program area is different from prior generations. The method for protecting
each portion of the OTP area is different. For additional details see Secure Silicon Region (OTP) on page 57.
Document Number: 001-98284 Rev. *J
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