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PDF S25FL064P Data sheet ( Hoja de datos )
| Número de pieza | S25FL064P | |
| Descripción | 64-Mbit 3.0 V SPI Flash Memory | |
| Fabricantes | Cypress | |
| Logotipo |  |
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S25FL064P
64-Mbit 3.0 V SPI Flash Memory
Distinctive Characteristics
Architectural Advantages
Single power supply operation
– Full voltage range: 2.7 to 3.6V read and write operations
Memory architecture
– Uniform 64-kB sectors
– Top or bottom parameter block (Two 64-kB sectors (top
or bottom) broken down into sixteen 4-kB sub-sectors
each)
– 256-byte page size
– Backward compatible with the S25FL064A device
Program
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Program operations are on a page by page basis
– Accelerated programming mode via 9V W#/ACC pin
– Quad Page Programming
Erase
– Bulk erase function
– Sector erase (SE) command (D8h) for 64-kB sectors
– Sub-sector erase (P4E) command (20h) for 4-kB sectors
– Sub-sector erase (P8E) command (40h) for 8-kB sectors
Cycling endurance
– 100,000 cycles per sector typical
Data retention
– 20 years typical
Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward
compatibility
One time programmable (OTP) area for permanent, secure
identification; can be programmed and locked at the factory
or by the customer
CFI (Common Flash Interface) compliant: allows host system
to identify and accommodate multiple flash devices
Process technology
– Manufactured on 90-nm MirrorBit® process technology
Package option
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 8-contact WSON package (6 8 mm)
– 24-ball BGA package (6 8 mm), 5 5 pin configuration
– 24-ball BGA package (6 8 mm), 6 4 pin configuration
Performance Characteristics
Speed
– Normal READ (Serial): 40 MHz clock rate
– FAST_READ (Serial): 104 MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80 MHz clock rate or
20 MB/s effective data rate
– QUAD I/O FAST_READ: 80 MHz clock rate or
40 MB/s effective data rate
Power saving standby mode
– Standby Mode 80 A (typical)
– Deep Power-Down Mode 3 A (typical)
Memory Protection Features
Memory protection
– W#/ACC pin works in conjunction with Status Register Bits
to protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in
status register configure parts of memory as read-only
Software Features
– SPI Bus Compatible Serial Interface
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00649 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 18, 2016
1 page  
S25FL064P
2. Connection Diagrams
Figure 2.1 16-pin Plastic Small Outline Package (SO)
Note
DNC = Do Not Connect (Reserved for future use)
HOLD#/IO3 1
VCC 2
DNC
DNC
DNC
DNC
3
4
5
6
CS#
SO/IO1
7
8
16 SCK
15 SI/IO0
14 DNC
13 DNC
12 DNC
11 DNC
10 GND
9 W#/ACC/IO2
Figure 2.2 8-contact WSON Package (6 x 8 mm)
CS#
SO/IO1
W#/ACC/IO2
1
2
WSON
3
8
7
6
VCC
HOLD#/IO3
SCK
GND 4
5 SI/IO0
Note
There is an exposed central pad on the underside of the USON package. This should not be connected to any voltage or signal line on the PCB. Connecting the central
pad to GND (VSS) is possible, provided PCB routing ensures 0 mV difference between voltage at the USON GND (VSS) lead and the central exposed pad.
Figure 2.3 6 x 8 mm 24-ball BGA Package, 5 x 5 Pin Configuration
12345
A
NC NC NC NC
B
NC
SCK GND VCC
NC
C
NC CS# NC W#/ACC/IO2 NC
D
NC SO/IO1 SI/IO0 HOLD#/IO3 NC
E
NC NC NC NC NC
Document Number: 002-00649 Rev. *I
Page 5 of 62
5 Page 
S25FL064P
7. Device Operations
All Cypress SPI devices accept and output data in bytes (8 bits at a time). The SPI device is a slave device that supports an inactive
clock while CS# is held low.
7.1 Byte or Page Programming
Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which
consists of four bytes plus data. The Page Program sequence accepts from 1 byte up to 256 consecutive bytes of data (which is the
size of one page) to be programmed in one operation. Programming means that bits can either be left at 0, or programmed from 1 to
0. Changing bits from 0 to 1 requires an erase operation.
7.2 Quad Page Programming
The Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed using 4 pins as inputs at the same
time, thus effectively quadrupling the data transfer rate, compared to the Page Program (PP) instruction. The Write Enable Latch
(WEL) bit must be set to a 1 using the Write Enable (WREN) command prior to issuing the QPP command.
7.3 Dual and Quad I/O Mode
The S25FL064P device supports Dual and Quad I/O operation when using the Dual/Quad Output Read Mode and the Dual/Quad I/
O High Performance Mode instructions. Using the Dual or Quad I/O instructions allows data to be transferred to or from the device at
two to four times the rate of standard SPI devices. When operating in the Dual or Quad I/O High Performance Mode (BBh or EBh
instructions), data can be read at fast speed using two or four data bits at a time, and the 3-byte address can be input two or four
address bits at a time.
7.4 Sector Erase / Bulk Erase
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array to 1. While bits can be
individually programmed from 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (SE) or array-wide (BE) level. In addition
to the 64-kB Sector Erase (SE), the S25FL064P device also offers 4-kB Parameter Sector Erase (P4E) and 8-kB Parameter Sector
Erase (P8E).
7.5 Monitoring Write Operations Using the Status Register
The host system can determine when a Write Register, program, or erase operation is complete by monitoring the Write in Progress
(WIP) bit in the Status Register. The Read from Status Register command provides the state of the WIP bit. In addition, the
S25FL064P device offers two additional bits in the Status Register (P_ERR, E_ERR) to indicate whether a Program or Erase
operation was a success or failure.
7.6 Active Power and Standby Power Modes
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the device is disabled, but
may still be in the Active Power mode until all program, erase, and Write Registers operations have completed. The device then
goes into the Standby Power mode, and power consumption drops to ISB. The Deep Power-Down (DP) command provides
additional data protection against inadvertent signals. After writing the DP command, the device ignores any further program or
erase commands, and reduces its power consumption to IDP.
Document Number: 002-00649 Rev. *I
Page 11 of 62
11 Page | ||
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| PDF Descargar | [ Datasheet S25FL064P.PDF ] | |
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