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What is SC92031L?

This electronic component, produced by the manufacturer "Silan Semiconductors", performs the same function as "10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER".


SC92031L Datasheet PDF - Silan Semiconductors

Part Number SC92031L
Description 10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER
Manufacturers Silan Semiconductors 
Logo Silan Semiconductors Logo 


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SC92031
10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS
CONTROLLER AND PHYSICAL LAYER
DESCRIPTION
The SC92031 is a highly-integrated and cost-effective single-chip
Fast Ethernet NIC controller. It fully complies with PCI 2.2 and IEEE
802.3u 100Base-T specifications. It supports both half-duplex and full -
duplex operation, as well as for full-duplex flow control. It also supports
Advanced Configuration Power management Interface (ACPI), PCI
power management and remote wake-up events including AMD Magic
Packet, Link Change, and Microsoft® wake-up frame.
The SC92031 provides glue less 32-bit bus master interface for PCI,
boot ROM interface, as well as physical media interface for 100BASE-
TX of IEEE 802.3u and 10BASE-T of 802.3. It also supports shared
Boot ROM pins & clock run pin.
The SC92031 supports Analog Auto-Power-down, that is, the analog
part of the SC92031 can be shut down temporarily according to user
requirement or when the SC92031 is in a power down state with the
wakeup function disabled.
PCI Vital Product Data (VPD) is also supported to provide the
information that uniquely identifies hardware. The information may
consist of part number, serial number, and other detailed information.
To provide cost down, the SC92031 is capable of using a 25MHz
crystal or OSC as its internal clock source.
The SC92031 includes a PCI and Expansion Memory Share Interface
for a boot ROM and can be used in diskless workstations, providing
maximum network security and ease of management.
The SC92031 provides a flexible multi-function mode to incorporate
other PCI master devices. When in multi-function mode, the SC92031
acts as an arbiter to distinguish LAN signals from those of other
devices.
QFP-100-14x20-0.65
LQFP-100-14x14-0.5
ORDERING INFORMATION
Device
Package
SC92031 QFP-100-14 X 20-0.65
SC92031L LQFP-100-14 X 14-0.5
APPLICATIONS
* 10/100Mbps PCI fast Ethernet
adaptor
FEATURES
* Integrated Fast Ethernet MAC, Physical layer and transceiver in one chip
* 10 Mbps and 100 Mbps data rates
* Both half duplex and full duplex available
* IEEE 802.3 compliant Auto-Negotiation
* Supports PCI multi-function capabilities
* PCI local bus
Ø Compliant to PCI Revision 2.2
Ø Supports PCI clock 15 MHz-40 MHz
Ø Supports PCI target fast back-to-back transaction
Ø Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.0 2004.08.03
Page 1 of 38

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SC92031L equivalent
SC92031
(Continued)
Pin No.
Symbol
Description
98, 10, 20, 31 C/BE3-0B PCI bus command and byte enables.
14 DEVSELB Device Select, target is driving to indicate the address is decoded.
11 FRAMEB Begin and duration of bus access, driven by master device.
PCI bus granted. This signal indicates that the PCI bus request of SC92031
85 GNTB
has been accepted.
PCI bus request, the SC92031 will assert this signal low to request the
86 REQB
ownership of the bus from the central arbiter.
Initialization Device Select. This pin allows the SC92031 to identify when
99 IDSEL
configuration read/write transactions are intended for it.
PCI interrupt request. It is asserted low when an interrupt condition occurs,
81
INTAB
as defined by the Interrupt Status, Interrupt Mask and Interrupt Enable
registers.
12
IRDYB
Master device is ready to data transaction.
13
TRDYB
Slave device is ready to data transaction.
Parity, this signal indicates even parity across AD31-0 and C/BE3-0
19
PAR
including the PAR pin. As a master, PAR is asserted during address and
write data phases. As a target, PAR is asserted during read data phases.
16
PERRB
Data parity error is detected, driven by the agent receiving data.
18
SERRB
Address parity error.
15
STOPB
The current target is requesting the master to stop the current transaction.
Power Management/Isolation Interface
Power Management Event, Open drain, active low. Used by the SC92031 to
87
PMEB
request a change in its current power management state and/or to indicate
that a power management event has occurred.
LAN WAKE-UP signal, This signal is used to inform the motherboard to
execute the wake-up process. The motherboard must support Wake-On-
71
LWAKE
LAN (WOL). There are 4 choices of output, including active high, active low,
positive pulse, and negative pulse, that may be asserted from the LWAKE
EEPROM Interface
pin.
This pin is used to notify the SC92031 of the existence of Aux. power during
initial power-on or a PCI reset. This pin should be pulled high to the Aux.
49
AUX
power via a resistor to detect the Aux. power. Doing so, will enable wakeup
support from ACPI D3 cold or APM power-down. If this pin is not pulled
EEPROM Interface
high, the SC92031 assumes that no Aux. power exists.
47
EECK
EEPROM chip serial clock
46
EEDI
EEPROM chip serial data in
45
EEDO
EEPROM chip serial data out
48
EECS
EEPROM chip select
(To be continued)
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.0 2004.08.03
Page 5 of 38


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Part Details

On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for SC92031L electronic component.


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Featured Datasheets

Part NumberDescriptionMFRS
SC92031The function is 10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER. Silan SemiconductorsSilan Semiconductors
SC92031LThe function is 10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER. Silan SemiconductorsSilan Semiconductors

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