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PDF GS8673EQ36BK Data sheet ( Hoja de datos )
| Número de pieza | GS8673EQ36BK | |
| Descripción | 72Mb SigmaQuad-IIIe Burst of 2 ECCRAM | |
| Fabricantes | GSI Technology | |
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GS8673EQ18/36BK-675/625/550/500
260-Ball BGA
Commercial Temp
Industrial Temp
72Mb SigmaQuad-IIIe™
Burst of 2 ECCRAM™
675 MHz–500 MHz
1.35V VDD
1.2V to 1.5V VDDQ
Features
• On-Chip ECC with virtually zero SER
• Configurable Read Latency (3.0 or 2.0 cycles)
• Simultaneous Read and Write SigmaQuad-IIIe™ Interface
• Separate I/O Bus
• Double Data Rate interface
• Burst of 2 Read and Write
• Pipelined read operation
• Fully coherent Read and Write pipelines
• 1.35V nominal VDD
• 1.2V JESD8-16A BIC-3 Compliant Interface
• 1.5V HSTL Interface
• ZQ pin for programmable output drive impedance
• ZT pin for programmable input termination impedance
• Configurable Input Termination
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package
–K: 5/6 RoHS-compliant package
–GK: 6/6 RoHS-compliant package
SigmaQuad-IIIe™ Family Overview
SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS8673EQ18/36BK SigmaQuad-IIIe ECCRAMs are
synchronous devices. They employ dual, single-ended master
clocks, CK and CK. These clocks are single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. CK and CK are used to control the address and control
input registers, as well as all output timing.
The KD and KD clocks are dual mesochronous (with respect to
CK and CK) input clocks that are used to control the data input
registers. Consequently, data input setup and hold windows
can be optimized independently of address and control input
setup and hold windows.
Each internal read and write operation in a SigmaQuad-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 4M x 18 has
2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles, etc. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
Parameter Synopsis
Speed Bin
Operating Frequency
Data Rate (per pin)
-675 675 / 450 MHz 1350 / 900 Mbps
-625 625 / 400 MHz 1250 / 800 Mbps
-550 550 / 375 MHz
1100 / 750 Mbps
-500 500 / 333 MHz 1000 / 666 Mbps
Note: Please contact GSI for availability of 714 MHz devices.
Read Latency
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
VDD
1.3V to 1.4V
1.3V to 1.4V
1.25V to 1.4V
1.25V to 1.4V
Rev: 1.06 5/2012
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
1 page  
GS8673EQ18/36BK-675/625/550/500
Pin Description (Continued)
Symbol
Description
MZT[1:0]
PZT[1:0]
MVQ
VDD
Input Termination Mode Select—Selects the termination mode used for all terminated inputs. Must be tied
High or Low.
MZT[1:0] = 00: disabled.
MZT[1:0] = 01: RT/2 Thevenin-equivalent (pull-up = RT, pull-down = RT).
MZT[1:0] = 10: RT Thevenin-equivalent (pull-up = 2*RT, pull-down = 2*RT).
MZT[1:0] = 11: reserved.
Input Termination Configuration Select—Selects which inputs are terminated. Must be tied High or Low.
PZT[1:0] = 00: Write Data only.
PZT[1:0] = 01: Write Data, Input Clocks.
PZT[1:0] = 10: Write Data, Address, Control.
PZT[1:0] = 11: Write Data, Address, Control, Input Clocks.
I/O Voltage Select—Indicates what voltage is supplied to the VDDQ pins. Must be tied High or Low.
MVQ = 0: Configure for 1.2V to 1.35V nominal VDDQ.
MVQ = 1: Configure for 1.5V nominal VDDQ.
Core Power Supply—1.35V nominal core supply voltage.
VDDQ
I/O Power Supply—1.2V to 1.5V nominal I/O supply voltage. Configurable via MVQ pin.
VREF Input Reference Voltage—Input buffer reference voltage.
VSS Ground
TCK JTAG Clock
TMS JTAG Mode Select—Weakly pulled High internally.
TDI JTAG Data Input—Weakly pulled High internally.
TDO JTAG Data Output
MCH Must Connect High—May be tied to VDDQ directly or via a 1kΩ resistor.
MCL Must Connect Low—May be tied to VSS directly or via a 1kΩ resistor.
NC
No Connect—There is no internal chip connection to these pins. They may be left unconnected, or tied High
or Low.
Not Used, Input—There is an internal chip connection to these input pins, but they are unused by the
NUI device. They are pulled Low internally. They may be left unconnected or tied Low. They should not be tied
High.
NUO
Not Used, Output—There is an internal chip connection to these output pins, but they are unused by the
device. Unused output pins are tri-stated internally. They should be left unconnected.
Type
Input
Input
Input
—
—
—
—
Input
Input
Input
Output
Input
Input
—
Input
Output
Rev: 1.06 5/2012
5/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
5 Page 
GS8673EQ18/36BK-675/625/550/500
CK, KD
CK, KD
Write1
(Notes 1)
NOP1
(Notes 2)
NOP2
LP NOP Timing Diagram
NOP3
(Note 3)
NOP4
NOP5
NOP6
Write2
(Note 4)
SA A
tKHAZTV(min)
tKHAZTV(max)
B
R
W
ADZT1
D A0
A1
tKHDZTV(min)
tKHDZTV(max)
B0 B1
Notes:
1. The Controller initiates Write1. The ECCRAM is enabling SA and D termination.
2. The Controller initiates two NOPs (NOP1 ~ NOP2) with ADZT1 High, to cause the ECCRAM to enter LP NOP Mode for two cycles.
The ECCRAM disables SA and D termination pull ups at ↑CK in NOP3, 2 cycles after sampling ADZT1 = 1 at ↑CK in NOP1.
The Controller drives SA, D Low during NOP1 ~ NOP6.
3. The Controller initiates four more NOPs (NOP3 ~ NOP6) with ADZT1 Low, to allow time for the ECCRAM to exit LP NOP Mode.
The ECCRAM enables SA and D termination pull ups at ↑CK in NOP5, 2 cycles after sampling ADZT1 = 0 at ↑CK in NOP3.
4. The Controller initiates Write2. The ECCRAM is enabling SA and D termination.
Rev: 1.06 5/2012
11/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
11 Page | ||
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