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What is GS82582DT21GE?

This electronic component, produced by the manufacturer "GSI Technology", performs the same function as "288Mb SigmaQuad-II+ Burst of 4 SRAM".


GS82582DT21GE Datasheet PDF - GSI Technology

Part Number GS82582DT21GE
Description 288Mb SigmaQuad-II+ Burst of 4 SRAM
Manufacturers GSI Technology 
Logo GSI Technology Logo 


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165-Bump BGA
Commercial Temp
Industrial Temp
GS82582DT21/39GE-675S/633S/550S
288Mb SigmaQuad-II+
Burst of 4 SRAM
Up to 675 MHz
1.8 V VDD
1.5 V I/O
Features
• For use with GSI FPGA-based Controller IP
• 3.0 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• 6/6 RoHS-compliant 165-bump BGA package
SigmaQuadFamily Overview
The GS82582DT21/39GE are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 301,989,888-bit (288Mb)
SRAMs. The GS82582DT21/39GE SigmaQuad SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS82582DT21/39GE SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B4 RAM is always two address pins
less than the advertised index depth (e.g., the 16M x 18 has a
4M addressable index).
tKHKH
Parameter Synopsis
-675S
1.48 ns
-633S
1.58 ns
-550S
1.81 ns
Rev: 1.01 4/2016
1/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology

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GS82582DT21GE equivalent
GS82582DT21/39GE-675S/633S/550S
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
SigmaQuad-II+ Burst of 4 SRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A Low on
the Read Enable pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Clocking
in a High on the Read Enable pin, R, begins a read port deselect cycle.
SigmaQuad-II+ Burst of 4 SRAM DDR Write
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R High causes chip disable. A Low on
the Write Enable pin, W, and a High on the Read Enable pin, R, begins a write cycle. W is always ignored if the previous command
was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and
finally by the next rising edge of K.
Special Functions
Byte Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 4-beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time BW0 BW1
Beat 1
01
Beat 2
10
Beat 3
00
Beat 4
10
D0–D8
Data In
Don’t Care
Data In
Don’t Care
D9–D17
Don’t Care
Data In
Data In
Data In
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Written
Unchanged
Beat 1
Byte 1
D0–D8
Byte 2
D9–D17
Unchanged
Written
Beat 2
Byte 1
D0–D8
Byte 2
D9–D17
Written
Written
Beat 3
Byte 1
D0–D8
Byte 2
D9–D17
Unchanged
Written
Beat 4
Rev: 1.01 4/2016
5/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology


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GS82582DT21GEThe function is 288Mb SigmaQuad-II+ Burst of 4 SRAM. GSI TechnologyGSI Technology

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