GS81314LT37GK Datasheet PDF - GSI Technology
Part Number | GS81314LT37GK | |
Description | 144Mb SigmaDDR-IVe Burst of 2 Single-Bank ECCRAM | |
Manufacturers | GSI Technology | |
Logo | ||
There is a preview and GS81314LT37GK download ( pdf file ) link at the bottom of this page. Total 30 Pages |
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260-Pin BGA
Com & Ind Temp
HSTL I/O
144Mb SigmaDDR-IVe™
Burst of 2 Single-Bank ECCRAM™
Up to 933 MHz
1.2V ~ 1.3V VDD
1.2V ~ 1.3V VDDQ
Features
• 4Mb x 36 and 8Mb x 18 organizations available
• Organized as a single logical memory bank
• 933 MHz maximum operating frequency
• 933 MT/s peak transaction rate (in millions per second)
• 67 Gb/s peak data bandwidth (in x36 devices)
• Common I/O DDR Data Bus
• Non-multiplexed SDR Address Bus
• One operation - Read or Write - per clock cycle
• No address/bank restrictions on Read and Write ops
• Burst of 2 Read and Write operations
• 5 cycle Read Latency
• On-chip ECC with virtually zero SER
• Loopback signal timing training capability
• 1.2V ~ 1.3V nominal core voltage
• 1.2V ~ 1.3V HSTL I/O interface
• Configuration registers
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaDDR-IVe™ Family Overview
SigmaDDR-IVe ECCRAMs are the Common I/O half of the
SigmaQuad-IVe/SigmaDDR-IVe family of high performance
ECCRAMs. Although similar to GSI's third generation of
networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe
family), these fourth generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS81314LT19/37GK SigmaDDR-IVe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaDDR-IVe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IVe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 8M x 18 has
4M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Speed Grade
-933
-800
Parameter Synopsis
Max Operating Frequency
933 MHz
800 MHz
Read Latency
5 cycles
5 cycles
VDD
1.25V to 1.35V
1.15V to 1.35V
Rev: 1.02 3/2016
1/42
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
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GS81314LT19/37GK-933/800
Symbol
PZT[1:0]
VDD
VDDQ
VREF
VSS
TCK
TMS
TDI
TDO
MCH
MCL
NC
NUI
NUIO
Description
ODT Configuration Select — Set the default ODT state for various combinations of input groups during
power-up and reset, when MZT[1:0] = 01 or 10. Must be tied High or Low.
PZT[1:0] = 00: enables ODT on write data only.
PZT[1:0] = 01: enables ODT on write data and input clocks.
PZT[1:0] = 10: enables ODT on write data, address, and control.
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.
Note: The ODT state for each input group can be changed at any time via the Configuration Registers.
Core Power Supply
I/O Power Supply
Input Reference Voltage — Input buffer reference voltage.
Ground
JTAG Clock — Weakly pulled Low internally.
JTAG Mode Select — Weakly pulled High internally.
JTAG Data Input — Weakly pulled High internally.
JTAG Data Output
Must Connect High — May be tied to VDDQ directly or via a 1k resistor.
Must Connect Low — May be tied to VSS directly or via a 1k resistor.
No Connect — There is no internal chip connection to these pins. They may be left unconnected, or tied/
driven High or Low.
Not Used Input — There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be
tied/driven High.
Not Used Input/Output — There is an internal chip connection to these I/O pins, but they are unused by the
device. The drivers are tri-stated internally. They are pulled Low internally. They may be left unconnected or
tied/driven Low. They should not be tied/driven High.
Type
Input
—
—
—
—
Input
Input
Input
Output
Input
Input
—
Input
I/O
Rev: 1.02 3/2016
5/42
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology
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