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XRS10L140 PDF Datasheet - SERIAL ATA II: 1:4 PORT MULTIPLIER - Exar Corporation

Part Number XRS10L140
Description SERIAL ATA II: 1:4 PORT MULTIPLIER
Manufacturers Exar Corporation 
Logo Exar Corporation Logo 
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XRS10L140 datasheet, circuit
PRELIMINARY
XRS10L140
SERIAL ATA II: 1:4 PORT MULTIPLIER
JUNE 2006
REV. P1.0.2
1.0 INTRODUCTION
The EXAR XRS10L140 is a Serial ATA port multiplier
designed for next generation enterprise class disk
array systems that use SATA mid-planes. The device
is targeted at low cost storage applications.
This function is used when one active host has to
communicate with multiple SATA drives. The
XRS10L140 supports up to 4 SATA drives and utilizes
the full bandwidth of the host connection.
The upstream ports of XRS10L140 can also be
attached to a port selector (XRS10L20) or a Serial
ATA Switch to provide redundancy in a more complex
topology.
The XRS10L140 includes enhanced features such as
staggered HDD spin-up, power management control,
hot plug capability and support for legacy software.
The XRS10L140 acts as a retimer, maintaining
independent signaling domains between the drives
themselves and the external interconnect.
The high-speed serial input features selectable
equalization adjustment and the high-speed serial
output features selectable pre-emphasis to
compensate for ISI (Inter-Symbol Interference) and
increase maximum cable distances.
XRS10L140 meets tight jitter budgets in SATA
applications. Exar's serial I/O technology enables
reliable data transmission over 1 meter or more of
FR-4 and 15 meters or more of unequalized copper
cable.
Host and drive port speeds can be mixed and
matched, based upon inherent data rate negotiation
present in the SATA II specifications.
The MDIO bus allows simple configuration of the
device.
To summarize, the XRT10L24 port multiplier device
allows the system designer to increase the number of
serial ATA connections in an enclosure that does not
have a sufficient number of serial ATA connections for
all of the drives in the enclosure.
OVERVIEW OF PORT MULTIPLIER LOGIC
XRS10L140 port multiplier is a multiplexer where one
active host connection is multiplexed to multiple
device connections. The XRS10L140 is an extensible
design that can support up to 4 device connections
and utilizes the full bandwidth of the host connection.
XRS10L140 uses four bits, known as the PM Port
field in all Serial ATA frame types, to route frames
between the selected host and the appropriate
device. PM ports 0 through 3 are valid device ports
within the 4-output XRS10L140, while PM port 15 is
designated for communication between the host and
the XRS10L140 itself. For host-to-device
transactions, the PM Port field is designated by the
host in order to specify which device the frame is
intended for. For device-to-host transactions, the
XRS10L140 fills in the PM Port field with the port
address of the device that is transmitting the frame.
STANDARDS COMPLIANCE
The XRS10L140 is compliant with the following
industry specifications:
Serial ATA, Revision 1.0a
Serial ATA II: Extensions to Serial ATA 1.0a,
Revision 1.2
Serial ATA II PHY Electrical Specifications,
Revision 1.0
Serial ATA II: Port Multiplier, Revision 1.2
APPLICATIONS
Serial ATA Enclosures
Other Serial ATA link replicator applications
Buffers for externally connected links
High density storage boxes
RAID Subsystems
FEATURES
GENERAL FEATURES
Five independent 3/1.5G SATA ports.
Supports 3/1.5G rate detection/speed negotiation.
Supports power down modes - Active, partial,
slumber and power down.
PORT MULTIPLIER LOGIC FEATURES
Low latency architecture.
Supports OOB signaling for SATA applications.
Internal OOB detectors for COMSAS, COMRESET/
COMINIT and COMWAKE.
TEST AND CONTROL FEATURES
Supports MDIO Bus.
Outputs for various failure modes.
Built-In self test mode through the MDIO bus.
Supports various loopback modes.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

1 page

XRS10L140 pdf, schematic
XRS10L140
PRELIMINARY
SERIAL ATA II: 1:4 PORT MULTIPLIER
REV. P1.0.2
HIGH SPEED I/O FEATURES
High speed outputs with selectable pre-emphasis to extend the link budgets.
High speed input equalization for improved signal integrity.
Compliant with SATA Gen2i & Gen2 specification.
Enables reliable data transmission over 1 meter or more of FR-4 and 15 meters or more of unequalized
copper cable.
Supports spread spectrum clocking to reduce EMI.
PHYSICAL FEATURES
CMOS 0.13 Micron Technology
Single 1.2 V Power Supply
-40°C to 85°C Industrial Temperature Range
2000 V ESD Rating on All Pins
No heatsink or airflow required
100-Pin QFP Package
APPLICATION EXAMPLE
The XRS10L140 is ideally suited for use within an external drive enclosure as a means of providing access to
up to four target devices per XRS10L140. This application is shown in Figure 1. Other applications for the
XRS10L140 include use in fixed-content or network attached storage systems, storage arrays, desktop
applications or entry-level servers, RAID storage or disk-to-disk backup.
FIGURE 1. SYSTEM BLOCK DIAGRAM FOR XRS10L140 IN A DRIVE ENCLOSURE APPLICATION
D R IV E EN C LO S U R E
X R T 10L140
PO R T M ULTIPLIER
X R T 10L140
PO R T M ULTIPLIER
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
2

2 Page

XRS10L140 equivalent
PRELIMINARY
XRS10L140
REV. P1.0.2
SERIAL ATA II: 1:4 PORT MULTIPLIER
3.0 FUNCTIONAL DESCRIPTION
A top-level view of the XRS10L140 is shown in Figure 2 outlining the interfaces to the device and the required
support components. The data path can be seen at the top of the device. This includes the output transmit and
input receive path at the top left, providing the upstream interface to the host, and the four output transmit and
input receive paths at the top right, providing the downstream interface to the target devices. The clocking,
control, and configuration interfaces are shown below the dotted line.
FIGURE 2. XRS10L140 INTERFACES
Serial ATA Upstream
Interface to HBAs
SiT_P0/SiT_N0 SOT_P/N[3:0]
SiR_P0/SiR_N0 SOR_P/N[3:0]
Serial ATA Downstream
Interface to HBAs
Control and
configuration
Interface
DRACT[3:0]
HBACT0
RESETB
PWRDNB
MDC
MDIO1
VDDA
RBIAS
Calibration Resistor
49.9 Ω ± 5%
CMU_REF_P/N
XOD
XOG
TCK
TDI
TDO1
TMS
TRST
Reference Clock
Crystal Oscillator Inputs
JTAG Interface
The XRS10L140 incorporates identical instantiations of a dual-channel Serial ATA II 3 Gbps PHY macro. This
common building block provides a uniform implementation with common characteristics and a common
register map, but provides a functional implementation of independent PHY blocks. Digital logic
implementations of Serial ATA link layer blocks along with port multiplier logic provide the remainder of the data
path within the XRS10L140. In addition, management and control interfaces including an MDIO interface for
register control, a JTAG interface for boundary scan purposes, and a resistor calibration circuit complete the
device. A block diagram of the XRS10L140 is shown in Figure 3.
FIGURE 3. XRS10L140 BLOCK DIAGRAM
SIR 0
S IT0
S ATA II
3G PHY
SATA II
L IN K
LAYER
RATE
ADJUST
F IF O
S ATA II
LIN K
LAYER
S ATA II
LIN K
LAYER
PORT
M ULTIP LIER
S ATA II
LIN K
LAYER
S ATA II
LIN K
LAYER
SA TA II
3G PHY
SA TA II
3G PHY
SA TA II
3G PHY
SA TA II
3G PHY
SOT0
SOR0
SOT1
SOR1
SOT2
SOR2
SOT3
SOR3
5

5 Page

XRS10L140 diode, scr
PRELIMINARY
XRS10L140
REV. P1.0.2
SERIAL ATA II: 1:4 PORT MULTIPLIER
device has issued an R_OK primitive to indicate successful frame reception. In this way, the R_OK status
handshake is interlocked from the device to the host.
If an error is detected during any part of the frame transfer, the XRS10L140 will ensure that the error condition
is propagated to the host and the device. If no error occurs during frame transfer, the XRS10L140 will not alter
the contents of the frame, or modify the CRC in any way.
3.5.1 Transmission from a Device to a Host
A device indicates a transmit to a host in the same way as would be done if the host and device were attached
directly. This transaction obeys the following procedure:
1. After receiving an X_RDY primitive from the device, the XRS10L140 will determine if the X bit is set in the
device port's PSCR (SError) register. The XRS10L140 will not issue an R_RDY primitive to the device until
this bit is cleared to zero.
2. The XRS10L140 will then receive the frame from the device. The XRS10L140 will fill in the PM Port field
with the port address of the transmitting device. The XRS10L140 will then check the CRC received from
the device, and if valid, it will recalculate the CRC based upon the new PM Port field. If the CRC calculated
from the device is incorrect, the XRS10L140 will corrupt the CRC sent to the host to ensure propagation of
the error condition
3. The XRS10L140 will issue an X_RDY primitive to the host to start the transmission of the frame to the host.
After the host issues an R_RDY primitive to the XRS10L140, the frame from the device, with the updated
CRC, will then be transmitted to the host. The XRS10L140 will not send an R_OK status primitive to the
device until the host has issued an R_OK primitive to indicate successful frame reception. In this way, the
R_OK status handshake will be interlocked from the device to the host.
If an error is detected during any part of the frame transfer, the XRS10L140 will ensure that the error condition
is propagated to the host and the device.
9

9 Page

XRS10L140 transistor, igbt
PRELIMINARY
XRS10L140
REV. P1.0.2
SERIAL ATA II: 1:4 PORT MULTIPLIER
5.2 Macro Registers
The registers outlined in this section are common to each of the three Serial ATA dual PHY macros as
described in the previous section. As such, each listed register is present in each of the 1, 2, and 3 MDIO
register spaces, and will perform the stated function on the specified Serial ATA lane.
The registers within each dual PHY macro are split into three sections:
Transmit/receive lane 0 registers:
Address range 000*****
PLL registers:
Address range 010*****
Bias generator registers:
Address range 011*****
ADDRESS
HEX
N.0000
N.0001
TABLE 9: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2, 3)
BIT(S)
NAME
R/W
DEFAULT
DESCRPTION
7:6 Reserved RO
5:4
Receive_Test0[1:0]
R/W
3:2 Transmit_Test0[1:0] R/W
1
selFourFive
R/W
0
SATAPCIEXB
R/W
7:3 RiseFall_Coef0[4:0] R/W
2:0
Transmit_Eq0[2:0]
R/W
-
00
00
1
1
00000
000
Reserved
PRBS checker control
00 = disable PRBS checkers
01 = enable 2^23-1 checkers
10 = enable 2^31-1 checkers
11 = enable 2^10-1 checkes
Test Pattern Control
00 = Use input data from DATAIN
01 = Generate 2^23-1 PRBS
10 = Generate 2^31-1 PRBS
11 = Generate 2^10-1 PRBS
0 = Output data is x8
1 = Output data is x10
Tx output swing booster bit
0 = boost swing by 10%
1 = nominal swing
Output rise/fall time coefficient
00000 = +0ps
11111 = +25ps
01001 = SATA 3G
00010 = SATA 1.5G
other = increases rise/fall times monotonically
between 0 and 25ps
Transmit equalization contro
000 = 0% transmit preemphasis
001 = 6.5% transmit preemphasis
010 = 13% transmit preemphasis
011 = 19.5% transmit preemphasis
100 = 26% transmit preemphasis
101 = 32.5% transmit preemphasis
110 = 39% transmit preemphasis
111 = 45.5% transmit preemphasis
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21 Page





Information Total 30 Pages
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