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PDF ADuM4135 Data sheet ( Hoja de datos )
| Número de pieza | ADuM4135 | |
| Descripción | High Voltage Isolated IGBT Gate Driver | |
| Fabricantes | Analog Devices | |
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Data Sheet
Single-/Dual-Supply, High Voltage Isolated
IGBT Gate Driver with Miller Clamp
ADuM4135
FEATURES
GENERAL DESCRIPTION
4 A peak drive output capability
Output power device resistance: <1 Ω
Desaturation protection
Isolated desaturation fault reporting
Soft shutdown on fault
Miller clamp output with gate sense input
Isolated fault and ready functions
Low propagation delay: 55 ns typical
Minimum pulse width: 50 ns
The ADuM4135 is a single-channel gate driver specifically
optimized for driving insulated gate bipolar transistors (IGBTs).
Analog Devices, Inc., iCoupler® technology provides isolation
between the input signal and the output gate drive.
The ADuM4135 includes a Miller clamp to provide robust
IGBT turn-off with a single-rail supply when the gate voltage
drops below 2 V. Operation with unipolar or bipolar secondary
supplies is possible, with or without the Miller clamp operation.
Operating temperature range: −40°C to +125°C
The Analog Devices chip scale transformers also provide
Output voltage range to 30 V
isolated communication of control information between the
Input voltage range from 2.3 V to 6 V
high voltage and low voltage domains of the chip. Information
Output and input undervoltage lockout (UVLO)
on the status of the chip can be read back from dedicated
Creepage distance: 7.8 mm minimum
outputs. Control of resetting the device after a fault on the
100 kV/µs common-mode transient immunity (CMTI)
20 year lifetime for 600 V rms or 1092 V dc working voltage
Safety and regulatory approvals (pending)
5 kV ac for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak (reinforced/basic)
APPLICATIONS
secondary is performed on the primary side of the device.
Integrated onto the ADuM4135 is a desaturation detection
circuit that provides protection against high voltage short-
circuit IGBT operation. The desaturation protection contains
noise reducing features such as a 300 ns masking time after a
switching event to mask voltage spikes due to initial turn-on.
An internal 500 µA current source allows low device count and
the internal blanking switch allows the addition of an external
MOSFET/IGBT gate drivers
current source if more noise immunity is needed.
PV inverters
Motor drives
Power supplies
The secondary UVLO is set to 11 V with common IGBT
threshold levels taken into consideration.
FUNCTIONAL BLOCK DIAGRAM
VSS1 1
VI+ 2
VI– 3
READY 4
1
FAULT 5
1
ADuM4135
UVLO
MASTER
LOGIC
PRIMARY
ENCODE
RESET 6
VDD1 7
VSS1 8
1
1
1
DECODE
NOTES
1. GROUNDS ON PRIMARY AND SECONDARY SIDE ARE
ISOLATED FROM EACH OTHER.
TSD
CLAMP
LOGIC
2V
2
DECODE
ENCODE
MASTER
LOGIC
SECONDARY
2
9V
2
UVLO
16 VSS2
2
15 GATE_SENSE
14 VOUT_ON
13 VDD2
12 VOUT_OFF
11 GND2
10 DESAT
9 VSS2
2
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADuM4135
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Resistance (Input Side to High-Side Output)1
Capacitance (Input Side to High-Side Output)1
Input Capacitance
Junction to Ambient Thermal Resistance
Junction to Case Thermal Resistance
Symbol Min Typ Max Unit Test Conditions/Comments
RI-O 1012 Ω
CI-O 2.0 pF
CI 4.0 pF
θJA 75.4 °C/W 4-layer printed circuit board (PCB)
θJC 35.4 °C/W 4-layer PCB
1 The device is considered a two-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
REGULATORY INFORMATION
The ADuM4135 is pending approval by the organizations listed in Table 3.
Table 3.
UL (Pending)
Recognized under UL 1577
Component Recognition Program1
Single Protection,
5000 V rms Isolation Voltage
File E214100
CSA (Pending)
Approved under CSA Component Acceptance Notice 5A
Basic insulation per CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2, 780 V rms (1103 V
peak) maximum working voltage
Reinforced Insulation per CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2, 390 V rms (551 V
peak) maximum working voltage
File 205078
VDE (Pending)
Certified according to VDE0884-102
Reinforced insulation, 849 V peak
Basic insulation, 849 V peak
File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM4135 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA).
2 In accordance with DIN V VDE V 0884-10, each ADuM4135 is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge
detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
5000
7.8 min
Minimum External Tracking (Creepage)
L(I02) 7.8 min
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.026 min
>400
II
Unit
V rms
mm
mm
mm
V
Test Conditions/Comments
1 minute duration
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. B | Page 5 of 17
5 Page 
Data Sheet
800
700
600 SOURCE RESISTANCE
500
400
300
200 SINK RESISTANCE
100
0
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 16. Typical Output Resistance (RDSON) vs. Temperature, VDD2 = 15 V,
250 mA Test
800
700
600 SOURCE RESISTANCE
500
400
300
200 SINK RESISTANCE
100
0
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 17. Typical Output Resistance (RDSON) vs. Temperature, VDD2 = 15 V,
1 A Test
ADuM4135
CH1 = VI+ (5V/DIV)
1
CH2 = VGATE (5V/DIV)
2
CH3 = RESET (5V/DIV)
3
CH1 5.0V BW
CH3 5.0V BW
CH2 5.0V BW
M 500ns A CH3 1.7V
200MSPS 5.0ns/pt
Figure 18. Example RESET to Output Valid
9
8
PEAK SINK IOUT
7
6
5
4 PEAK SOURCE IOUT
3
2
1
0
12 14.5
17 19.5
22 24.5
OUTPUT SUPPLY VOLTAGE (V)
Figure 19. Typical Peak Output Current vs. Output Supply Voltage,
2 Ω Series Resistance (IOUT is the Current Going into/out of the Device Gate)
Rev. B | Page 11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADuM4135.PDF ] | |
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