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PDF ADuM4150 Data sheet ( Hoja de datos )
| Número de pieza | ADuM4150 | |
| Descripción | SPIsolator Digital Isolator | |
| Fabricantes | Analog Devices | |
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Data Sheet
5 kV, 6-Channel, SPIsolator Digital
Isolator for SPI with Delay Clock
ADuM4150
FEATURES
Supports up to 40 MHz SPI clock speed in delay clock mode
Supports up to 17 MHz SPI clock speed in 4-wire mode
4 high speed, low propagation delay, SPI signal isolation
channels
2 data channels at 250 kbps
Delayed compensation clock line
20-lead SOIC_IC with 8.3 mm creepage
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/µs
Safety and regulatory approvals
UL recognition per UL 1577
5000 V rms for 1 minute SOIC long package
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak
APPLICATIONS
Industrial programmable logic controllers (PLC)
Sensor isolation
GENERAL DESCRIPTION
The ADuM41501 is a 6-channel, SPIsolator™ digital isolator
optimized for isolated serial peripheral interfaces (SPIs). Based
on the Analog Devices, Inc., iCoupler® chip scale transformer
technology, the low propagation delay in the CLK, MO/SI,
MI/SO, and SS SPI bus signals supports SPI clock rates of up to
17 MHz. These channels operate with 13 ns propagation delay
and 1 ns jitter to optimize timing for SPI.
The ADuM4150 isolator also provides two additional independent
low data rate isolation channels, one channel in each direction.
Data in the slow channels is sampled and serialized for a 250 kbps
data rate with 2.5 µs of jitter.
The ADuM4150 supports a delay clock output on the master
side of the device. This output can be used with an additional
clocked port on the master to support 40 MHz clock performance.
See the Delay Clock section for more information.
FUNCTIONAL BLOCK DIAGRAM
VDD1 1
GND1 2
MCLK 3
MO 4
MI 5
MSS 6
ADuM4150
ENCODE
ENCODE
DECODE
ENCODE
VIA 7
VOB 8
DCLK 9
GND1 10
CONTROL
BLOCK
CLK
DELAY
DECODE
DECODE
ENCODE
DECODE
CONTROL
BLOCK
Figure 1.
20 VDD2
19 GND2
18 SCLK
17 SI
16 SO
15 SSS
14 VOA
13 VIB
12 NIC
11 GND2
Table 1. Related Products
Product
ADuM3150
ADuM3151/ADuM3152/
ADuM3153
ADuM3154
ADuM4151/ADuM4152/
ADuM4153
ADuM4154
Description
3.75 kV, high speed, clock delayed
SPIsolator
3.75 kV, multichannel SPIsolator
3.75 kV, multiple slave SPIsolator
5 kV, multichannel SPIsolator
5 kV, multiple slave SPIsolator
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADuM4150
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 4. Switching Specifications
Parameter
MCLK, MO, SO
SPI Clock Rate
Data Rate Fast (MO, SO)
Propagation Delay
Pulse Width
Pulse Width Distortion
Codirectional Channel Matching1
Jitter, High Speed
MSS
Data Rate Fast
Propagation Delay
Pulse Width
Pulse Width Distortion
Setup Time2
Jitter, High Speed
DCLK3
Data Rate
Propagation Delay
Pulse Width Distortion
Pulse Width
Clock Delay Error
Jitter
VIA, VIB
Data Rate Slow
Propagation Delay
Pulse Width
Jitter, Low Speed
VIx4 Minimum Input Skew5
A Grade
B Grade
Symbol Min Typ Max Min Typ Max Unit
Test Conditions/Comments
SPIMCLK
DRFAST
tPHL, tPLH
PW
PWD
tPSKCD
JHS
12.5
1
8.3
40
30
12.5
3
3
1
12.5 MHz
40 Mbps Within PWD limit
20 ns
50% input to 50% output
ns Within PWD limit
3 ns |tPLH − tPHL|
3 ns
ns
DRFAST
tPHL, tPLH
PW
PWD
MSSSETUP
JHS
12.5
1.5
1
40
30
12.5
3
10
1
40 Mbps Within PWD limit
30 ns
50% input to 50% output
ns Within PWD limit
3 ns |tPLH − tPHL|
ns
ns
40 40 MHz
tPHL, tPLH
60
40 ns
tPMCLK + tPSO + 3 ns
PWD 3 3 ns |tPLH − tPHL|
PW 12 12 ns Within PWD limit
DCLKERR −4 +2.4 +9 −3 +2.5 +8 ns
tPDCLK − (tPMCLK + tPSO)
JDCLK
1
1 ns
DRSLOW
tPHL, tPLH
PW
JLS
tVIx SKEW
0.1
4
10
250
2.6 0.1
4
2.5
10
250 kbps Within PWD limit
2.6 µs
50% input to 50% output
µs Within PWD limit
2.5 µs
ns
1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3 tPMCLK is the propagation delay of the MCLK signal from Side 1 to Side 2. tPSO is the propagation delay of the SO signal from Side 2 to Side 1. tPDCLK is the difference
between the DCLK signal and the round trip propagation delay.
4 VIx = VIA or VIB.
5 An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Rev. B | Page 5 of 21
5 Page 
Data Sheet
ADuM4150
PACKAGE CHARACTERISTICS
Table 10.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
IC Junction-to-Ambient Thermal Resistance
Symbol Min Typ Max Unit Test Conditions/Comments
RI-O 1012 Ω
CI-O 1.0 pF f = 1 MHz
CI 4.0 pF
θJA 46 °C/W Thermocouple located at center of package underside
1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM4150 is approved by the organizations listed in Table 11. See Table 16 and the Insulation Lifetime section for recommended
maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 11.
UL
Recognized Under UL 1577 Component
Recognition Program1
5000 V rms Single Protection
File E214100
CSA
Approved under CSA Component Acceptance
Notice 5A
Basic insulation per CSA 60950-1-07+A1+A2
and IEC 60950-12nd Ed+A1+A2., 800 V rms
(1131 V peak) maximum working voltage3
Reinforced Insulation per CSA 60950-1-
07+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2,
400 V rms (565 V peak) maximum working
voltage
Reinforced insulation (2MOPP) per IEC 60601-1
Ed.3.1, 250 V rms (353 V peak) maximum
working
File 205078
VDE
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Reinforced insulation, 849 V peak
File 2471900-4880-0001
1 In accordance with UL 1577, each model is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 µA).
2 In accordance with DIN V VDE V 0884-10, each model is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection limit = 5 pC).
The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.
3 Use at working voltages above 400 VAC RMS shortens lifetime of the isolator significantly. See Table 16 for recommended maximum working voltages under ac and dc conditions.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 12.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
Symbol
L(I01)
L(I02)
CTI
Value
5000
8.3
8.3
0.017
>400
II
Unit
V rms
mm min
mm min
mm min
V
Conditions
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. B | Page 11 of 21
11 Page | ||
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