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A290011B PDF Datasheet - AMIC

Part Number A290011B
Description Boot Sector Flash Memory
Manufacturers AMIC 
Logo AMIC Logo 
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A290011B datasheet, circuit
Preliminary
A29001B/A290011B Series
128K X 8 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Document Title
128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
June 16, 2016
Remark
Preliminary
PRELIMINARY (June, 2016, Version 0.0)
AMIC Technology, Corp.
AMIC reserves the right to change products and specifications discussed herein without notice.

1 page
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A290011B pdf, schematic
A29001B/A290011B Series
Preliminary
128K X 8 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Features
„ 5.0V ± 10% for read and write operations
„ Access time:
- 55ns (max.)
„ Current:
- 20mA typical active read current
- 30mA typical program/erase current
- 6μA typical CMOS standby
„ Flexible sector architecture
- 8 Kbyte/ 4 KbyteX2/ 16 Kbyte/ 32 KbyteX3 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
„ Top or bottom boot block configurations available
„ Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors
- Embedded Program algorithm automatically writes
and verifies bytes at specified addresses
„ Minimum 100,000 program/erase cycles per sector
„ 20-year data retention at 125ºC
- Reliable operation for the life of the system
„ Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
- Superior inadvertent write protection
„ Data Polling and toggle bits
- Provides a software method of detecting completion
of program or erase operations
„ Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
„ Hardware reset pin (RESET )
- Hardware method to reset the device to reading array
data (not available on A290011B)
„ Industrial operating temperature range: -40°C to +85°C
for – U
„ Package options
- 32-pin P-DIP, PLCC or TSOP
- All Pb-free (Lead-free) products are RoHS2.0 compliant
General Description
The A29001B is a 5.0 volt-only Flash memory organized as
131,072 bytes of 8 bits each. The A29001B offers the
RESET function, but it is not available on A290011B. The
128 Kbytes of data are further divided into seven sectors for
flexible sector erase capability. The 8 bits of data appear on
I/O0 - I/O7 while the addresses are input on A0 to A16. The
A29001B is offered in 32-pin PLCC, PDIP and TSOP
packages. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply.
Additional 12.0 volt VPP is not required for in-system write
or erase operations. However, the A29001B can also be
programmed in standard EPROM programmers.
The A29001B has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O6 toggle bit, the
A29001B has a second toggle bit, I/O2, to indicate whether
the addressed sector is being selected for erase. The
A29001B also offers the ability to program in the Erase
Suspend mode. The standard A29001B offers access time
of 55ns allowing high-speed microprocessors to operate
without wait states. To eliminate bus contention the device
has separate chip enable ( CE ), write enable ( WE ) and
output enable ( OE ) controls.
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29001B is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the
programming and erase operations. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times
the program pulse widths and verifies proper program
margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.
The host system can detect whether a program or erase
operation is complete by reading the I/O7 ( Data Polling)
and I/O6 (toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array data
or accept another command.
PRELIMINARY (June, 2016, Version 0.0)
1
AMIC Technology, Corp.

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A290011B equivalent
A29001B/A290011B Series
Absolute Maximum Ratings*
Ambient Operating Temperature ……... -55°C to +125°C
Storage Temperature ............................. -65°C to +150°C
Ground to VCC……………………….……… -2.0V to 6.5V
Output Voltage (Note 1) …………………… -2.0V to 6.5V
A9, OE & RESET (Note 2)………………. -2.0V to 11.5V
All other pins (Note 1) ………………………. -2.0V to 6.5V
Output Short Circuit Current (Note 3) ……………. 200mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot
VSS to -2.0V for periods of up to 20ns. Maximum DC
voltage on output and I/O pins is VCC +0.5V. During
voltage transitions, outputs may overshoot to VCC
+1.5V for periods up to 20ns.
2. Minimum DC input voltage on A9 pins is -0.5V. During
voltage transitions, A9, OE and RESET may
overshoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 and OE is +11.5V
which may overshoot to 12.5V for periods up to 20ns.
(RESET is N/A on A290011B)
3. No more than one output is shorted at a time.
Duration of the short circuit should not be greater than
one second.
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
Operating Ranges
Commercial Devices
Ambient Temperature (TA) ………………… 0°C to +70°C
Extended Range Devices
Ambient Temperature (TA) ……………… -40°C to +85°C
VCC Supply Voltages
VCC for ± 10% devices . . . . . . . . . . . . . . +4.5V to +5.5V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is composed of latches that store the commands,
along with the address and data information needed to
execute the command. The contents of the register serve
as inputs to the internal state machine. The state
machine outputs dictate the function of the device. The
appropriate device bus operations table lists the inputs
and control levels required, and the resulting output. The
following subsections describe each of these operations
in further detail.
Table 1. A29001B/A290011B Device Bus Operations
Operation
CE OE
Read
Write
CMOS Standby
TTL Standby
Output Disable
Reset
Temporary Sector Unprotect (Note)
L
L
VCC ± 0.5 V
H
L
X
X
L
H
X
X
H
X
X
WE RESET A0 – A16
(N/A A290011B)
HH
AIN
LH
AIN
X VCC ± 0.5 V
X
X VCC ± 0.5 V
X
HH
X
XL
X
X VID
X
I/O0 - I/O7
DOUT
DIN
High-Z
High-Z
High-Z
High-Z
X
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 10.5 ± 1.0V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: 1. See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.
2. This function is not available on A290011B.
PRELIMINARY (June, 2016, Version 0.0)
4
AMIC Technology, Corp.

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A290011B diode, scr
Command Definitions
Writing specific address and data commands or
sequences into the command register initiates device
operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the improper
sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE or
CE , whichever happens later. All data is latched on the
rising edge of WE or CE , whichever happens first. Refer
to the appropriate timing diagrams in the "AC
Characteristics" section.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm. After the device accepts an Erase Suspend
command, the device enters the Erase Suspend mode.
The system can read array data using the standard read
timings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. After
completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See "Erase Suspend/Erase
Resume Commands" for more information on this mode.
The system must issue the reset command to re-enable
the device for reading array data if I/O5 goes high, or while
in the autoselect mode. See the "Reset Command"
section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing
diagram.
Reset Command
Writing the reset command to the device resets the device
to reading array data. Address bits are don't care for this
command. The reset command may be written between
the sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence before
programming begins. This resets the device to reading
array data (also applies to programming in Erase Suspend
mode). Once programming begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be
written to return to reading array data (also applies to
autoselect during Erase Suspend).
If I/O5 goes high during a program or erase operation,
writing the reset command returns the device to reading
array data (also applies during Erase Suspend).
A29001B/A290011B Series
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected. The
Command Definitions table shows the address and data
requirements. This method is an alternative to that shown
in the Autoselect Codes (High Voltage Method) table,
which is intended for PROM programmers and requires
VID on address bit A9.
The autoselect command sequence is initiated by writing
two unlock cycles, followed by the autoselect command.
The device then enters the autoselect mode, and the
system may read at any address any number of times,
without initiating another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX03h retrieves the
continuation code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to the Sector
Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is
not required to provide further controls or timings. The
device automatically provides internally generated
program pulses and verify the programmed cell margin.
The Command Definitions table shows the address and
data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses
are no longer latched. The system can determine the
status of the program operation by using I/O7 or I/O6. See
"Write Operation Status" for information on these status
bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Programming is allowed in
any sequence and across sector boundaries. A bit cannot
be programmed from a "0" back to a "1 ". Attempting to do
so may halt the operation and set I/O5 to "1", or cause the
Data Polling algorithm to indicate the operation was
successful. However, a succeeding read will show that the
data is still "0". Only erase operations can convert a "0" to
a "1".
PRELIMINARY (June, 2016, Version 0.0)
8
AMIC Technology, Corp.

9 Page
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A290011B transistor, igbt
Timing Waveforms for Program Operation
A29001B/A290011B Series
Addresses
Program Command Sequence (last two cycles)
tWC tAS
555h
PA
CE
OE
WE
Data
tAH
tGHWL tCH
tWP
tCS tWPH
tDS tDH
A0h PD
VCC
tVCS
Read Status Data (last two cycles)
PA PA
tWHWH1
Status
DOUT
Note : PA = program addrss, PD = program data, Dout is the true data at the program address.
PRELIMINARY (June, 2016, Version 0.0)
20
AMIC Technology, Corp.

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