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A25LQ16 PDF Datasheet - AMIC

Part Number A25LQ16
Description Dual/Quad-I/O Serial Flash Memory
Manufacturers AMIC 
Logo AMIC Logo 
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A25LQ16 datasheet, circuit
A25LQ16 Series
16Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory
with 100MHz Uniform 4KB Sectors
Document Title
16Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory with 100MHz Uniform
4KB Sectors
Revision History
Rev. No.
0.0
1.0
1.1
1.2
History
Initial issue
Final version release
Change tSE(typ.) from 150ms to 0.08s
Change tSE(max.) from 280ms to 0.2s
Change tBE(typ,) from 0.7s to 0.5s
P50: Change ICC6 & ICC7(max.) from 15mA to 25mA
Issue Date
August 17, 2011
August 29, 2011
November 15, 2011
Remark
Preliminary
Final
March 29, 2012
(March, 2012, Version 1.2)
AMIC Technology Corp.

1 page
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A25LQ16 pdf, schematic
A25LQ16 Series
16Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory
with 100MHz Uniform 4KB Sectors
FEATURES
„ Family of Serial Flash Memories
- A25LQ16: 16M-bit /2M-byte
„ Flexible Sector Architecture with 4KB sectors
- Sector Erase (4K-bytes) in 70ms (typical)
- Block Erase (64K-bytes) in 0.5s (typical)
- Program/Erase Suspend & Resume
„ Page Program (up to 256 Bytes) in 1.5ms (typical)
„ 2.7 to 3.6V Single Supply Voltage
„ Dual input / output instructions resulting in an equivalent
clock frequency of 200MHz:
- FAST_READ_DUAL_OUTPUT Instruction
- FAST_READ_DUAL_INPUT_OUTPUT Instruction
- Dual Input Fast Program (DIFP) Instruction
„ Quad input / output instructions resulting in an equivalent
clock frequency of 400MHz:
- FAST_READ_QUAD_ OUTPUT Instruction
- FAST_READ_QUAD_INPUT_OUTPUT Instruction
- Quad Input Fast Program (QIFP) Instruction
„ SPI Bus Compatible Serial Interface
„ 100MHz Clock Rate (maximum)
„ Deep Power-down Mode 15µA (Max.)
„ Advanced Protection Features
- Software and Hardware Write-Protect
- Top/Bottom, 4KB Complement Array Protection
„ Additional 64-byte user-lockable, one-time programmable
(OTP) area
„ 16Mbit Flash memory
- Uniform 4-Kbyte Sectors
- Uniform 64-Kbyte Blocks
„ Electronic Signatures
- JEDEC Standard Two-Byte Signature
A25LQ16: (4015h)
- RES Instruction, One-Byte, Signature, for backward
compatibility
A25LQ16: (14h)
„ Package options
- 8-pin SOP (150/209mil), 8-pin DIP (300mil) or 8-pin WSON
(6*5mm)
- All Pb-free (Lead-free) products are RoHS compliant
GENERAL DESCRIPTION
The A25LQ16 is 16M bit Serial Flash Memory, with advanced
write protection mechanisms, accessed by a high speed
SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The memory is organized as 32 blocks, each containing 16
sectors. Each sector is composed of 16 pages. Each page is
256 bytes wide. Thus, the whole memory can be viewed as
consisting of 8,192 pages, or 2,097,152 bytes.
The whole memory can be erased using the Chip Erase
instruction, a block at a time, using Block Erase instruction, or a
sector at a time, using the Sector Erase instruction.
Pin Configurations
„ SOP8 Connections
„ DIP8 Connections
„ WSON8 Connections
A25LQ16
S
DO (IO1)
W (IO2)
VSS
1
2
3
4
8 VCC
7 HOLD (IO3)
6C
5 DI (IO0)
A25LQ16
S
DO (IO1)
W (IO2)
VSS
1
2
3
4
8 VCC
7 HOLD (IO3)
6C
5 DI (IO0)
A25LQ16
S
DO (IO1)
W (IO2)
VSS
1
2
3
4
8 VCC
7 HOLD (IO3)
6C
5 DI (IO0)
(March, 2012, Version 1.2)
1 AMIC Technology Corp.

2 Page
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A25LQ16 equivalent
SPI MODES
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from the
A25LQ16 Series
falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 1,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0) Æ Mode 0
– C remains at 1 for (CPOL=1, CPHA=1) Æ Mode 3
Figure 1. SPI Modes Supported
CPOL CPHA
Mode 0 0
0C
Mode 3 1
1C
DIO
DO
MSB
MSB
(March, 2012, Version 1.2)
4 AMIC Technology Corp.

5 Page
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A25LQ16 diode, scr
A25LQ16 Series
Table 1-2. Protected Area Sizes (CMP=1)
A25LQ16
Status Register Content
(16M-Bit) Memory Protection
SEC TB BP2 BP1 BP0
XX
0
0
0
Block(s)
0 - 31
Addresses
000000h – 1FFFFFh
Density(Byte)
2MB
Portion
All
00
0
0
1
0 - 30
000000h – 1EFFFFh
1984KB
Lower 31/32
00
0
1
0
0 – 29
000000h – 1DFFFFh
1920KB
Lower 15/16
00
0
1
1
0 – 27
000000h – 1BFFFFh
1792KB
Lower 7/8
00
1
0
0
0 – 23
000000h – 17FFFFh
1536KB
Lower 3/4
00
1
0
1
0 – 15
000000h – 1FFFFFh
1MB
Lower 1/2
01
0
0
1
1 - 31
010000h – 1FFFFFh
1984KB
Upper 31/32
01
0
1
0
2 – 31
020000h – 1FFFFFh
1920KB
Upper 15/16
01
0
1
1
4 – 31
040000h – 1FFFFFh
1792KB
Upper 7/8
01
1
0
0
8 – 31
080000h – 1FFFFFh
1536KB
Upper 3/4
01
1
0
1
16 - 31
100000h – 1FFFFFh
1MB
Upper 1/2
XX
1
1
X
None
None
None
None
10
0
0
1
0 - 31
000000h – 1FEFFFh
2044KB
Lower 511/512
10
0
1
0
0 - 31
000000h – 1FDFFFh
2040KB
Lower 255/256
10
0
1
1
0 - 31
000000h – 1FBFFFh
2032KB
Lower 127/128
10
1
0
X
0 -31
000000h – 1F7FFFh
2016KB
Lower 63/64
11
0
0
1
1 – 31
001000h – 1FFFFFh
2044KB
Upper 511/512
11
0
1
0
1 – 31
002000h – 1FFFFFh
2040KB
Upper 255/256
11
0
1
1
1 – 31
004000h – 1FFFFFh
2032KB
Upper 127/128
11
1
0
X
1 – 31
008000h – 1FFFFFh
2016KB
Upper 63/64
Note:
1. X = don’t care
2. When CMP is 1, the device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) bits
are 1.
(March, 2012, Version 1.2)
8 AMIC Technology Corp.

9 Page
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A25LQ16 transistor, igbt
A25LQ16 Series
Read Data Bytes at Higher Speed by Dual Output (FAST_READ_DUAL_OUTPUT)
The FAST_READ_DUAL_OUTPUT (3Bh) instruction is
similar to the FAST_READ (0Bh) instruction except the data
is output on two pins, IO0 and IO1, instead of just DO. This
allows data to be transferred from the A25LQ16 at twice the
rate of standard SPI devices.
Similar to the FAST_READ instruction, the
FAST_READ_DUAL_OUTPUT instruction can operate at the
highest possible frequency of fC (See AC Characteristics).
This is accomplished by adding eight “dummy” clocks after
the 24-bit address as shown in figure 9. The dummy clocks
allow the device’s internal circuits additional time for setting
up the initial address. The input data during the dummy
clocks is “don’t care”. However, the IO0 and IO1 pins should
be high-impedance prior to the falling edge of the first data
out clock.
Figure 9. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction (3Bh)
24-Bit Address
IO0 23 22 21 3 2 1 0
MSB
High Impedance
IO1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte
DIO switches from input to output
IO0 7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
IO1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
MSB
MSB
MSB
Data Out 1
Data Out 2
Data Out 3
Data Out 4
Note: Address bits A23 to A21 are Don’t Care, for A25LQ16.
(March, 2012, Version 1.2)
20 AMIC Technology Corp.

21 Page





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