M25P10
1 Mbit Low Voltage Paged Flash Memory
With 20 MHz Serial SPI Bus Interface
PRELIMINARY DATA
s 1 Mbit PAGED Flash Memory
s 128 BYTE PAGE PROGRAM IN 3 ms TYPICAL
s 256 Kbit SECTOR ERASE IN 1 s TYPICAL
s BULK ERASE IN 2 s TYPICAL
s SINGLE 2.7 V to 3.6 V SUPPLY VOLTAGE
s SPI BUS COMPATIBLE SERIAL INTERFACE
s 20 MHz CLOCK RATE AVAILABLE
s SUPPORTS POSITIVE CLOCK SPI MODES
s DEEP POWER DOWN MODE (1 µA TYPICAL)
s ELECTRONIC SIGNATURE
s 10,000 ERASE/PROG CYCLES PER SECTOR
s 20 YEARS DATA RETENTION
s –40 TO 85°C TEMPERATURE RANGE
DESCRIPTION
The M25P10 is an 1 Mbit Paged Flash Memory
fabricated with STMicroelectronics High
Endurance CMOS technology. The memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q).
The device connected to the bus is selected when
the chip select input (S) goes low. Data is clocked
in during the low to high transition of clock C, data
8
1
SO8 (MN)
150 mil width
8
1
SO8 (MW)
200 mil width
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
D
C
S
W
HOLD
M25P10
VSS
Q
AI03744
June 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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Figure 6. Block Diagram
HOLD
W
S
C
D
Q
Control Logic
I/O Shift Register
High Voltage
Generator
Address Register
and Counter
Data
Register
1FF80h
Status
1FFFFh
An
0000h
An + 7Fh
128 Bytes
X Decoder
007Fh
M25P10
Size of the
Read only
Memory
area
AI03747
Table 5. Protected Area Sizes
BP1
BP0
00
01
10
11
Software Protected Area
none
Upper quarter = Sector 3
Upper half = Sectors 2 & 3
Whole memory= Sectors 0, 1, 2 & 3
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