PIC18F46K40 Datasheet PDF - Microchip
| Part Number | PIC18F46K40 | |
| Description | Memory Programming Specification | |
| Manufacturers | Microchip | |
| Logo |  |
|
|
There is a preview and PIC18F46K40 download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
Preview 1 page No Preview Available !
PIC18(L)F2X/4XK40
PIC18(L)F2X/4XK40 Memory Programming Specification
1.0 OVERVIEW
This programming specification describes an SPI-based programming method for the PIC18(L)F2X/4XK40 family of
microcontrollers. Section 3.0 “Programming Algorithms” describes the programming commands, programming
algorithms and electrical specifications which are used in that particular programming method. Appendix B contains
individual part numbers, device identification and checksum values, pinout and packaging information and Configuration
Words.
Note 1: This is a SPI-compatible programming method with 8-bit commands.
2: The low-voltage entry code is now 32 clocks and MSb first, unlike previous PIC18 devices which had 33
clocks and LSb first.
1.1 Programming Data Flow
Nonvolatile Memory (NVM) programming data can be supplied by either the high-voltage In-Circuit Serial
Programming™ (ICSP™) interface or the low-voltage In-Circuit Serial Programming (ICSP) interface. Data can be
programmed into the Program Flash Memory (PFM), Data Flash Memory (EEPROM), dedicated “user ID” locations and
the Configuration Words.
1.2 Write and/or Erase Selection
Erasing or writing is selected according to the command used to begin operation (see Table 3-1). The terminologies
used in this document related to erasing/writing to the program memory are defined in Table 1-1 and are detailed below.
TABLE 1-1: PROGRAMMING TERMS
Term
Definition
Programmed Cell
Erased Cell
Erase
Write
Program
A memory cell at logic ‘0’
A memory cell at logic ‘1’
Change memory cell from a ‘0’ to a ‘1’
Change memory cell from a ‘1’ to a ‘0’
Generic erase and/or write
1.2.1 ERASING MEMORY
Memory is erased by row or in bulk, where ‘bulk’ includes many subsets of the total memory space. The duration of the
erase is determined by the size of program memory. All Bulk ICSP Erase commands have minimum VDD requirements,
which are higher than the Row Erase and write requirements.
1.2.2 WRITING MEMORY
Memory is written one row at a time. Multiple Load Data for NVM commands are used to fill the row data latches. The
duration of the write can be determined either internally or externally.
1.2.3 MULTI-WORD PROGRAMMING INTERFACE
Program Flash Memory (PFM) panels include up to a 64-word (one row) programming interface. Refer to Table 3-3 for
row size of erase and write operations for the PIC18(L)F2X/4XK40 family. The row to be programmed must first be
erased either with a Bulk Erase or a Row Erase.
2014 Microchip Technology Inc.
DS40001772A-page 1
|
| |
 
PIC18(L)F2X/4XK40
2.1 User ID Location
A user may store identification information (user ID) in eight designated locations. The user ID locations are mapped to
20 0000h-20 000Fh. Each location is 16 bits in length. It is recommended that the Most Significant nibble of each ID be
Fh. In doing so, if the user code inadvertently tries to execute from the ID space, the ID data will execute as a NOP. Code
protection has no effect on these memory locations. Each location may be read with code protection enabled or
disabled.
2.2 Device/Revision ID
The 16-bit device ID word is located at 3F FFFEh and the 16-bit revision ID is located at 3F FFFCh. These locations are
read-only and cannot be erased or modified.
REGISTER 2-1: DEVICEID: DEVICE ID REGISTER
R R R RR
DEV15
bit 15
DEV14
DEV13
DEV12
DEV11
R
DEV10
R
DEV9
R
DEV8
bit 8
R
DEV7
bit 7
R
DEV6
R
DEV5
R
DEV4
R
DEV3
R
DEV2
R
DEV1
R
DEV0
bit 0
Legend:
R = Readable bit
‘1’ = Bit is set
0’ = Bit is cleared
x = Bit is unknown
bit 15-0
DEV<15:0>: Device ID bits
REGISTER 2-2:
R
1
bit 15
REVISIONID: REVISION ID REGISTER
R R RR
0 10
RR
MJRREV<5:2>
R
bit 8
RR
MJRREV<1:0>
bit 7
R RR R R R
MNRREV<5:0>
bit 0
Legend:
R = Readable bit
‘1’ = Bit is set
0’ = Bit is cleared
x = Bit is unknown
bit 15-12
bit 11-6
bit 5-0
Read as ‘1010’
These bits are fixed with value ‘1010’ for all devices in this programming specification.
MJRREV<5:0>: Major Revision ID bits
These bits are used to identify a major revision. A major revision is indicated by an all layer revision
(A0, B0, C0, etc...).
Revision A = 6’b00_0000
MNRREV<5:0>: Minor Revision ID bits
These bits are used to identify a minor revision.
Revision A0 = 6’b00_0000
2014 Microchip Technology Inc.
DS40001772A-page 5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for PIC18F46K40 electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ PIC18F46K40.PDF Datasheet ] | |
Share Link :
Electronic Components Distributor
|
An electronic components distributor is a company that sources, stocks, and sells electronic components to manufacturers, engineers, and hobbyists. |
| SparkFun Electronics | Allied Electronics | DigiKey Electronics | Arrow Electronics |
| Mouser Electronics | Adafruit | Newark | Chip One Stop |
Featured Datasheets
| Part Number | Description | MFRS |
| PIC18F46K40 | The function is Memory Programming Specification. Microchip | |
Semiconductors commonly used in industry:
1N4148 |
BAW56 |
1N5400 |
NE555 | | ||
Quick jump to:
PIC1
1N4
2N2
2SA
2SC
74H
BC
HCF
IRF
KA | ||