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PDF CW24C256 Data sheet ( Hoja de datos )
| Número de pieza | CW24C256 | |
| Descripción | 128Kbit and 256Kbit Serial I2C Bus EEPROM | |
| Fabricantes | ChipsWinner | |
| Logotipo |  |
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CW 24C 93C SOP/TSSOP 8205A
CW24C128/CW24C256
128Kbit and 256Kbit Serial I²C Bus EEPROM
DESCRIPTION
PIN CONFIGURATION
The CW24C128/256 is Electrically Erasable PROM. The device
is organized as one block of 16384/32768 x 8-bit memory with
2-wire serial interface. Low-voltage design permits operation
A0 1
A1 2
8 VCC
7 WP
down to 1.8V, with standby and active currents of only 1μA and
NC 3
6 SCL
1mA respectively. The CW24C128/256 also has a page write
GND 4
5 SDA
capability for up to 64 bytes of data.
(Top View)
FEATURES
● Wide Voltage Operation VCC= 1.8V to 5.5V
● Low-power technology
- 1mA Active Current (Typical)
- 1μA Standby Current (Typical)
● Internally Organized:
- CW24C128, 16384x8 (128K bits)
- CW24C256, 32768x8 (256K bits)
● Two-wire Serial Interface, Fully I²C Bus Compatible
● 400kHz (1.8V, 2.7V, 5V) Compatibility
● Schmitt Trigger Inputs for Noise Suppression
● Write Protect Pin for Hardware Data Protection
● Self-timed Write Cycle (5 ms max)
● Byte and Multi-byte Write
● Page Write, 64-byte Page(CW24C128/256)
● Byte, Random and Sequential Read Mode
● Automatic Address Increment
● ESD protection > 2.5kV
● High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
● DIP8LˈSOP8LPackages
● Pb-free finish available, RoHS compliant
APPLICATIONS
● Intelligent Instrument
● Industrial Controller
● Household Appliance
● Automotive Electronics
● Computer/Notebook
● Communication
1
1 page  
SCL
tSU.STA
SDA_IN
SDA_OUT
tF
tLOW
tHD.STA
CW24C128/CW24C256
tHIGH
tLOW
tR
tHD.DAT
tSU.DAT
tSU.STO
tAA tDH
tBUF
Figure 2. Bus Timing
SCL
SDA
8th BIT
ACK
tWR(1)
STOP
CONDITION
START
CONDITION
NOTE 1. The write cycle time tWR is the time from a valid stop condition of a write
sequence to the end of the internal clear/write cycle.
Figure 3. Write Cycle Timing
5
5 Page 
CW24C128/CW24C256
DETAILED OPERATING INFORMATION(CONTINUED)
1. Current Address Read
The internal data word address counter maintains the last address accessed during the last
read or write operation, incremented by one. This address stays valid between operations as
long as the chip power is maintained. The address "roll over" during read is from the last byte
of the last memory page to the first byte of the first page. The address "roll over" during write is
from the last byte of the current page to the first byte of the same page.
Once the device address with the read/write select bit set to "1" is clocked in and acknowl-
edged by the EEPROM, the current address data word is serially clocked out. The microcon-
troller does not respond with an input "0" but does generate a following stop condition (see
Figure 12).
S
T
A
R
T
DEVICE
ADDRESS
R
E
A
D
DATA
S
T
O
P
SDA LINE
M
S
B
L RA
S/C
BWK
Figure 12. Current Address Read
N
O
A
C
K
2. Random Read
A random read requires a "dummy" byte write sequence to load in the data word address.
Once the device address word and data word address are clocked in and acknowledged by
the EEPROM, the microcontroller must generate another start condition. The microcontroller
now initiates a current address read by sending a device address with the read/write select bit
high. The EEPROM acknowledges the device address and serially clocks out the data word.
The microcontroller does not respond with a "0" but does generate a following stop condition
(see Figure 13).
SW
TR
AI
R DEVICE T
T ADDRESS E
1st,2nd WORD
ADDRESS(n)
S
T
A
R
T
DEVICE
ADDRESS
R
E
A
D
DATA( n )
S
T
O
P
SDA LINE
M
S
B
L R AM
S / CS
BWK B
LA M
SC S
BK B
LRA
S/C
BWK
DUMMY WRITE
Figure 13. Random Read
N
O
A
C
K
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CW24C256.PDF ] | |
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