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PDF ALT6720 Data sheet ( Hoja de datos )
| Número de pieza | ALT6720 | |
| Descripción | LTE Linear PAM | |
| Fabricantes | ANADIGICS | |
| Logotipo |  |
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FEATURES
• LTE Compliant
• 4th Generation HELPTM technology
• High Efficiency (LTE MPR = 0 dB):
• 36 % @ POUT = +27.5 dBm
• 23 % @ POUT = +16 dBm
• 16 % @ POUT = +7 dBm
• Low Quiescent Current: 3 mA
• Low Leakage Current in Shutdown Mode: <5 µA
• Internal Voltage Regulator
• Integrated “daisy chainable” directional coupler
with CPLIN and CPLOUT port.
• Internal DC block on IN/OUT RF ports
• Optimized for a 50 Ω System
• 1.8 V Control Logic
• RoHS Compliant Package, 260 oC MSL-3
ALT6720
HELP4TM E800 (Band 20)
LTE Linear PAM
Data Sheet - Rev 2.3
ALT6720
M45 Package
10 Pin 3 mm x 3 mm x 1 mm
Surface Mount Module
APPLICATIONS
• Band 20 LTE Wireless Devices
PRODUCT DESCRIPTION
The ALT6720 HELP4TM PA is a 4th generation HELPTM
product for LTE devices operating in E800 MHz Band
20. This PA incorporates ANADIGICS’ HELP4TM
technology to deliver exceptional efficiency at low
power levels and low quiescent current without the
need for external voltage regulators or converters.
The device is manufactured using advanced InGaP-
PlusTM HBT technology offering state-of-the-art
reliability, temperature stability, and ruggedness.
Three selectable bias modes that optimize efficiency
for different output power levels and a shutdown
mode with low leakage current increase handset
talk and standby time. A “daisy chainable” directional
coupler is integrated in the module, thus eliminating
the need of an external coupler. The self-contained
3 mm x 3 mm x 1 mm surface mount package
incorporates matching networks optimized for output
power, efficiency, and linearity in a 50 Ω system.
VBATT
RFIN
VMODE2
VMODE1
VEN
1
2
3
4
5
GND at Slug (pad)
10 VCC
CPL
9 RFOUT
Bias Control
Voltage Regulation
8 CPLIN
7 GND
6 CPLOUT
Figure 1: Block Diagram
03/2012
1 page  
ALT6720
APPLICATION INFORMATION
To ensure proper performance, refer to all related
Application Notes on the ANADIGICS web site:
http://www.anadigics.com
to the VMODE pins. The Bias Control table below lists
the recommended modes of operation for various
applications.
Shutdown Mode
The power amplifier may be placed in a shutdown mode
by applying logic low levels (see Operating Ranges
table) to the VEN, VMODE1 and VMODE2 voltages.
Bias Modes
The power amplifier may be placed in either Low,
Medium or High Bias modes by applying the
appropriate logic level (see Operating Ranges table)
Three operating modes are recommended to optimize
current consumption. High Bias/High Power operating
mode is for POUT levels > 16 dBm. At ~16 dBm - 7 dBm,
the PA could be switched to Medium Power Mode. For
POUT levels < ~7 dBm, the PA could be switched to Low
Power Mode for extremely low current consumption.
APPLICATION
Low power
(Low Bias Mode)
Med power
(Medium Bias Mode)
High power
(High Bias Mode)
Shutdown
POUT
LEVELS
Table 5: Bias Control
BIAS
MODE
VEN
VMODE1
VMODE2
VCC
≤ +7 dBm
Low +1.8 V +1.8 V +1.8 V 3.2 - 4.35 V
≥ +7 dBm
≤ +16 dBm
Low
+1.8 V +1.8 V 0 V 3.2 - 4.35 V
≥ +16 dBm High +1.8 V 0 V
0 V 3.2 - 4.35 V
- Shutdown 0 V 0 V 0 V 3.2 - 4.35 V
VBATT
> 3.2 V
> 3.2 V
> 3.2 V
> 3.2 V
VBATT
C6 C1 C5
2.2 µF 0.01µF 100 pF
RFIN
VMODE2
VMODE1
VEN
(1)
GND at slug
1 VBATT
2 RFIN
3 VMODE2
4 VMODE1
5 VEN
VCC 10
RFOUT 9
CPLIN 8
GND 7
CPLOUT 6
Notes:
(1) Rise and Fall time on VEN Control Signal must be ≤ 1.0 µS.
C3
330 pF
C2
0.01 µF
VCC
C4
2.2 µF ceramic
CPLIN
RFOUT
CPLOUT
Figure 3: Evaluation Board Schematic
5 Data Sheet - Rev 2.3
03/2012
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet ALT6720.PDF ] | |
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