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PDF ALT5020 Data sheet ( Hoja de datos )
| Número de pieza | ALT5020 | |
| Descripción | LTE Linear PAM | |
| Fabricantes | ANADIGICS | |
| Logotipo |  |
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FEATURES
• LTE Compliant
• High Efficiency (LTE waveform):
• 42% @ POUT = +27.7 dBm
• Optimized for SMPS Supply
• Low Leakage Current in Shutdown Mode: <5 µA
• Internal Voltage Regulator
• Integrated “daisy chainable” directional coupler
with CPLIN and CPLOUT Ports
• Optimized for a 50 Ω System
• Internal DC blocks on IN/OUT RF ports
• 1.8 V Control Logic
• RoHS Compliant Package, 260 oC MSL-3
APPLICATIONS
• Wireless Handsets and Data Devices for:
• LTE (B20)
ALT5020
High Efficiency
UMTS E800 (Band 20)
LTE Linear PAM
ADvanced product information - Rev 0.0
ALT5020
10 Pin 3 mm x 3 mm x 0.9 mm
Surface Mount Module
PRODUCT DESCRIPTION
The ALT5020 PA is designed to provide highly linear
output for LTE handsets and data devices with high
efficiency at high power mode. This ANADIGICS PA
can be used with an external switch mode power VBATT
supply (SMPS) to improve its efficiency and reduce
current consumption further at high and low output
powers. The device is manufactured on an advanced
InGaP HBT MMIC technology offering state-of-the- RFIN
art reliability, temperature stability, and ruggedness.
There are three selectable bias modes that optimize
efficiency for different output power levels, and a
shutdown mode with low leakage current, which VMODE2
increases handset talk and standby time. The self-
contained 3 mm x 3 mm x 0.9 mm surface mount
package incorporates matching networks optimized for
output power, efficiency, and linearity in a 50 Ω system.
VMODE1
1
2
3
4
GND at Slug (pad)
10 VCC
CPL 9 RFOUT
Bias Control
Voltage Regulation
8 CPLIN
7 GND
VEN 5
Figure 1: Block Diagram
6 CPLOUT
09/2013
1 page  
ALT5020
APPLICATION INFORMATION
To ensure proper performance, refer to all related
Application Notes on the ANADIGICS web site:
http://www.anadigics.com
logic level (see Operating Ranges table) to VMODE1,2.
The Bias Control table lists the recommended modes
of operation for various applications.
Shutdown Mode
The power amplifier may be placed in a shutdown
mode by applying logic low levels (see Operating
Ranges table) to the VENABLE and VMODE voltages.
Bias Modes
The power amplifier may be placed in either a Low,
Medium or High Bias mode by applying the appropriate
Three operating modes are available to optimize
current consumption. High Bias/High Power operating
mode is for POUT levels > 15 dBm. At around 16 dBm
output power, the PA should be “Mode Switched” to
Medium power mode for lowest quiescent current
consumption. The PA should be switched to Low Bias/
Low Power mode at ~<7 dbm.
Vcontrols
Venable/Vmode(s)
On Sequence Start
T_0 N =0 µ
ON Sequence
Rise/Fall Max 1µS
Defined at 10% to 90%
of Min/Max Voltage
Off Sequence Start
T_0FF= 0µ
OFF Sequence
RFIN
notes 1,2
VEN
VCC
note 1
T_0N+1µS
T_0N+3 µS
T_0FF+2µS T_0FF+3µS
Referenced After 90% of Rise
Time
Referenced Before10% of Fall
Time
Figure 3: Recommended ON/OFF Timing Sequence
Notes:
(1) Level might be changed after RF is ON.
(2) RF OFF defined as PIN ≤ -30 dBm.
(3) Switching simultaneously between VMODE and VEN is not recommended.
5 advanced product information - Rev 0.0
09/2013
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ALT5020.PDF ] | |
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