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What is CLC420AJP?

This electronic component, produced by the manufacturer "National Semiconductor", performs the same function as "High-Speed/ Voltage Feedback Op Amp".


CLC420AJP Datasheet PDF - National Semiconductor

Part Number CLC420AJP
Description High-Speed/ Voltage Feedback Op Amp
Manufacturers National Semiconductor 
Logo National Semiconductor Logo 


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N
Comlinear CLC423
94MHz, Single Supply Voltage Feedback Op Amp
August 1996
General Description
The Comlinear CLC423 is a wideband voltage-feedback
operational amplifier that is uniquely designed to provide high
performance from a single power supply. The CLC423 provides
near rail-to-rail operation and the common-mode input range
includes the negative rail. The CLC423 offers plenty of head-
room for single-supply applications as evidenced by its 4.3Vpp
output voltage from a single 5V supply.
Fabricated with a high-speed complementary bipolar process, the
CLC423 delivers a wide 94MHz unity-gain bandwidth, 7.5ns
rise/fall time and 150V/µs slew rate. For single supply applications
such as video distribution or desktop multimedia, the CLC423
offers low 0.35%, 0.55° differential gain and phase errors.
The CLC423 provides high signal fidelity with -74/-94dBc 2nd/3rd
harmonics (1Vpp, 1MHz, RL=150). Combining this high fidelity
performance with CLC423’s quick 46ns settling time to 0.1%
makes it an excellent choice for ADC buffering.
With its traditional voltage-feedback architecture and high-speed
performance, the CLC423 is the perfect choice for composite
signal conditioning circuit functions such as active filters,
integrators, differentiators, simple gain blocks and buffering.
Features
s Single +5V supply
s Input includes VEE
s 94MHz unity-gain bandwidth
s -74/-94dBc HD2/HD3
s 60mA output current
s 7.5ns rise/fall time (1Vpp)
s 46ns settling time to 0.1%
Applications
s Video ADC driver
s Desktop multimedia
s Single supply cable driver
s Instrumentation
s Video cards
s Wireless IF amplifiers
s Telecommunications
Frequency Response vs. Vout
Av = +2V/V
1Vpp
2Vpp
4Vpp
Typical Application
Single +5V Supply operation
Vin
50
+5V
0.1µF
+
CLC423
-
6.8µF +
150
Vo
250
250
NOTE: Vin = 0.15V to 2.3V
© 1996 National Semiconductor Corporation
Printed in the U.S.A.
1 10
Frequency (MHz)
Single Supply Response
VCC 5
4
3
2
1
VEE 0
Time (100ns/div)
100
Pinout
DIP & SOIC
VEE
http://www.national.com

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CLC420AJP equivalent
Load Termination
Since the CLC423 design has been optimized for Single
Supply Operation, it is more capable of sourcing rather
than sinking current. For optimum performance, the load
should be tied to VEE. When the load is tied to VEE, the
output always sources current.
Output Overdrive Recovery
When the output range of an amplifier is exceeded, time
is required for the amplifier to recover from this over
driven condition. Figure 5 illustrates the overload
recovery of the CLC423 when the output is overdriven.
An input was applied in an attempt to drive the output to
twice the supply rails (2 (VCC -VEE) = 10V), but the
output limits. An inverting gain topolgy was used, see
Figure 2. As indicated, the CLC423 recovers within
25ns on the rising edge and within 10ns on the falling
edge.
p
Non-inverting gain applications:
s Connect Rg directly to ground.
s Make R1, R2, R6, and R7 equal to Zo.
s Use R3 to isolate the amplifier from reactive
loading caused by the transmission line, or
by parasitics.
Inverting gain applications:
s Connect R3 directly to ground.
s Make the resistors R4, R6, and R7 equal to Zo.
s Make R5 II Rg = Zo.
The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is
needed. Use C6 to match the output transmission line
over a greater frequency range. C6 compensates for the
increase of the amplifier’s output impedance with
frequency.
Input Power Dissipation
Follow these steps to determine the power consumption
of the CLC423:
Output
Time (50ns/div)
Figure 5: Overdrive Recovery
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC423
will improve stability and settling performance. The
Frequency Response vs. CL plot, in the typical
performance section, gives the recommended series
resistance value for optimum flatness at various
capacitive loads.
Transmission Line Matching
One method for matching the characteristic impedance
(Zo) of a transmission line or cable is to place the
appropriate resistor at the input or output of the amplifier.
Figure 6 shows typical inverting and non-inverting circuit
configurations for matching transmission lines.
1. Calculate the quiescent (no-load) power:
Pamp = ICC (VCC - VEE)
2. Calculate the RMS power at the output stage:
Po = (VCC - Vload) (Iload), where Vload and
Iload are the RMS voltage and current across
the external load.
3. Calculate the total RMS power:
Pt = Pamp + Po
The maximum power that the DIP and SOIC packages
can dissipate at a given temperature is illustrated in
Figure 7. The power derating curve for any package can
be derived by utilizing the following equation:
where:
(175° − Tamb )
θJA
Tamb = Ambient temperature (°C)
θja = Thermal resistance, from junction to ambient, for a
given package (°C/W)
1.0
AJP
0.8
AJE
0.6
R1 Z0
R3
C6
+ Z0 Vo
V1
+
-
R2
CLC423
-
R6
R7
R4 Z0
Rg Rf
V2
+
-
R5
Figure 6: Transmission Line Matching Fi
0.4
0.2
0
0 20 40 60 80 100 120 140 160 180
Ambient Temperature (°C)
Figure 7: Power Derating Curves
5 http://www.national.com


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