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PDF LM555C Data sheet ( Hoja de datos )
| Número de pieza | LM555C | |
| Descripción | Timer | |
| Fabricantes | National Semiconductor | |
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February 1995
LM555 LM555C Timer
General Description
The LM555 is a highly stable device for generating accurate
time delays or oscillation Additional terminals are provided
for triggering or resetting if desired In the time delay mode
of operation the time is precisely controlled by one external
resistor and capacitor For astable operation as an oscilla-
tor the free running frequency and duty cycle are accurately
controlled with two external resistors and one capacitor
The circuit may be triggered and reset on falling waveforms
and the output circuit can source or sink up to 200 mA or
drive TTL circuits
Features
Y Direct replacement for SE555 NE555
Y Timing from microseconds through hours
Y Operates in both astable and monostable modes
Y Adjustable duty cycle
Y Output can source or sink 200 mA
Y Output and supply TTL compatible
Y Temperature stability better than 0 005% per C
Y Normally on and normally off output
Applications
Y Precision timing
Y Pulse generation
Y Sequential timing
Y Time delay generation
Y Pulse width modulation
Y Pulse position modulation
Y Linear ramp generator
Schematic Diagram
C1995 National Semiconductor Corporation TL H 7851
TL H 7851 – 1
RRD-B30M115 Printed in U S A
1 page  
Applications Information
MONOSTABLE OPERATION
In this mode of operation the timer functions as a one-shot
(Figure 1 ) The external capacitor is initially held discharged
by a transistor inside the timer Upon application of a nega-
tive trigger pulse of less than 1 3 VCC to pin 2 the flip-flop is
set which both releases the short circuit across the capaci-
tor and drives the output high
When the reset function is not in use it is recommended
that it be connected to VCC to avoid any possibility of false
triggering
Figure 3 is a nomograph for easy determination of R C
values for various time delays
NOTE In monostable operation the trigger should be driv-
en high before the end of timing cycle
FIGURE 1 Monostable
TL H 7851 – 5
The voltage across the capacitor then increases exponen-
tially for a period of t e 1 1 RA C at the end of which time
the voltage equals 2 3 VCC The comparator then resets
the flip-flop which in turn discharges the capacitor and
drives the output to its low state Figure 2 shows the wave-
forms generated in this mode of operation Since the charge
and the threshold level of the comparator are both directly
proportional to supply voltage the timing internal is inde-
pendent of supply
FIGURE 3 Time Delay
TL H 7851 – 7
ASTABLE OPERATION
If the circuit is connected as shown in Figure 4 (pins 2 and 6
connected) it will trigger itself and free run as a multivibrator
The external capacitor charges through RA a RB and dis-
charges through RB Thus the duty cycle may be precisely
set by the ratio of these two resistors
VCC e 5V
TIME e 0 1 ms DIV
Top Trace Input 5V Div
Middle Trace Output 5V Div
TL H 7851 – 6
RA e 9 1 kX
C e 0 01 mF
Bottom Trace Capacitor Voltage 2V Div
FIGURE 2 Monostable Waveforms
During the timing cycle when the output is high the further
application of a trigger pulse will not effect the circuit so
long as the trigger input is returned high at least 10 ms be-
fore the end of the timing interval However the circuit can
be reset during this time by the application of a negative
pulse to the reset terminal (pin 4) The output will then re-
main in the low state until a trigger pulse is again applied
FIGURE 4 Astable
TL H 7851 – 8
In this mode of operation the capacitor charges and dis-
charges between 1 3 VCC and 2 3 VCC As in the triggered
mode the charge and discharge times and therefore the
frequency are independent of the supply voltage
5
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| PDF Descargar | [ Datasheet LM555C.PDF ] | |
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