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PDF UFX6000 Data sheet ( Hoja de datos )
| Número de pieza | UFX6000 | |
| Descripción | USB 2.0 Hi-Speed Graphics Controller | |
| Fabricantes | SMSC | |
| Logotipo |  |
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UFX6000
USB 2.0 Hi-Speed Graphics
Controller with VGA, HDMI/DVI,
and Digital RGB Interfaces
PRODUCT FEATURES
Highlights
Single-Chip Hi-Speed USB 2.0 Graphics Adapter
USB 2.0 Device Controller with Integrated USB 2.0
PHY
Highly Efficient Compression Algorithm
HDMI/DVI Display Connectivity via Integrated
HDMI/DVI Controller/PHY
VGA Display Connectivity via Integrated Video DAC
Support for External Display Interface IC’s via
Digital RGB Interface
High Performance DDR2 SDRAM Controller with
Integrated DDR2 PHY
Target Applications
USB to Video Adapters
Docking Stations, USB Port Replicators
Thin Clients
USB Monitors and Projectors
Embedded Systems
Features
USB 2.0 Device Controller
— Fully compliant with Universal Serial Bus Specification
Revision 2.0
— Operates in HS (480 Mbps) mode
— Supports Control, Bulk-Out, and Interrupt-In endpoints
— Supports vendor specific commands
— Integrated USB 2.0 PHY
— Integrated USB termination pull-up/pull-down resistors
— Short circuit protection of USB differential signals
Datasheet
Graphics Subsystem
— Integrated HDMI/DVI Controller and PHY
– Complies with DVI specification v1.0
– Complies with HDMI specification v1.3
– S/PDIF and I2S inputs for HDMI audio
(2-channel uncompressed PCM)
– Master I2C interface for DDC connection
— Integrated Triple 10-bit Video DAC with VGA output
— Digital RGB Interface
– 12/15-bit double data rate digital RGB
– 24-bit single data rate digital RGB
— Supports up to 2048x1152 (QWXGA) with 32-bit color
— 8-bit and 16-bit color support
— Supports display cloning and extending
— Standard and wide screen aspect ratios
— Complies with VESA auto display identification
— Gamma correction
— Color Look-Up Table (CLUT)
— Triple-buffered animations
— Graphics Engine
– Optimized algorithms for static and dynamic content
– I2C controller
DDR2 SDRAM Controller
— 16-bit data bus, 13-bit address bus
— JEDEC DDR2 compliant (JESD79-2E)
— Integrated DDR2 SDRAM PHY
Power
— Reduced power operating modes
— Supports bus-powered and self-powered operation
Miscellaneous Features
— Optional EEPROM controller
— IEEE 1149.1 (JTAG) boundary scan TAP controller
Software
— Microsoft Windows® XP/Vista/7 drivers
Packaging & Environmental
— 225-ball LFBGA, RoHS compliant package
— Commercial temperature range (0°C to +70°C)
SMSC UFX6000
DATASHEET
Revision 1.4 (06-24-13)
1 page  
USB 2.0 Hi-Speed Graphics Controller with VGA, HDMI/DVI, and Digital RGB Interfaces
Datasheet
List Of Tables
Table 2.1 USB Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2.2 Digital RGB Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2.3 RGB / DDR Mode Mapping Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2.4 VDAC Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2.5 DDR2 Memory Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 2.6 HDMI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2.7 EEPROM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 2.8 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 2.9 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 2.10 I/O Power Pins, Core Power Pins, and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 2.11 No-Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 2.12 225-LFBGA Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 2.13 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 4.1 EEPROM Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 4.2 Configuration Flags 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 4.3 EEPROM Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 5.1 Package Thermal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5.2 SUSPEND Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5.3 Typical High-Speed Operational Supply Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 5.4 I/O Buffer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5.5 Video DAC - DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 5.6 Power-On Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 5.7 nRESET Power-On Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 5.8 nRESET Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 5.9 Video DAC - AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 5.10 Digital RGB Timing Values - DDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 5.11 Digital RGB Timing Values - SDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 5.12 EEPROM Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 5.13 JTAG Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 5.14 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 6.1 225-LFBGA Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 7.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SMSC UFX6000
5
DATASHEET
Revision 1.4 (06-24-13)
5 Page 
NUM PINS
NAME
Blue Pixel
Data Channel
Bit 3
DDR RGB
1 Data 4
General
Purpose I/O
19
Blue Pixel
Data Channel
Bit 2
DDR RGB
1 Data 5
General
Purpose I/O
18
Blue Pixel
Data Channel
Bit 1
DDR RGB
1 Data 6
General
Purpose I/O
17
Blue Pixel
Data Channel
Bit 0
1 General
Purpose I/O
16
Green Pixel
Data Channel
Bit 7
1 General
Purpose I/O
15
USB 2.0 Hi-Speed Graphics Controller with VGA, HDMI/DVI, and Digital RGB Interfaces
Datasheet
Table 2.2 Digital RGB Pins (continued)
SYMBOL
BUFFER
TYPE
DESCRIPTION
VDATAB3
RGB
Blue Pixel Video Data Bit 3, RGB Single Ended
Mode.
VD4 RGB Used in RGB DDR Mode, refer to Table 2.3.
GPIO19
VDATAB2
IS/O8/
OD8
(PU)
Note 2.1
RGB
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Blue Pixel Video Data Bit 2, RGB Single Ended
Mode.
VD5 RGB Used in RGB DDR Mode, refer to Table 2.3.
GPIO18
VDATAB1
IS/O8/
OD8
(PU)
Note 2.1
RGB
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Blue Pixel Video Data Bit 1, RGB Single Ended
Mode.
VD6 RGB Used in RGB DDR Mode, refer to Table 2.3.
GPIO17
VDATAB0
IS/O8/
OD8
(PU)
Note 2.1
RGB
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Blue Pixel Video Data Bit 0, RGB Single Ended
Mode.
GPIO16
VDATAG7
IS/O8/
OD8
(PU)
Note 2.1
RGB
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Green Pixel Video Data Bit 7, RGB Single Ended
Mode.
GPIO15
IS/O8/
OD8
(PU)
Note 2.1
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
SMSC UFX6000
11
DATASHEET
Revision 1.4 (06-24-13)
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UFX6000.PDF ] | |
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