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PDF IS2015S Data sheet ( Hoja de datos )
| Número de pieza | IS2015S | |
| Descripción | Bluetooth 4.1 Mono Audio Speaker SOC | |
| Fabricantes | ISSC | |
| Logotipo |  |
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Brochure
IS2015S
Bluetooth 4.1 Mono Audio Speaker SOC
GENERAL DESCRIPTION
IS2015S is a compact, highly integrated,
CMOS single-chip RF and baseband IC for
preliminary Bluetooth v4.1 with Enhanced
Data Rate 2.4GHz applications. This chip is
fully compliant with Bluetooth specification
and completely backward-compatible with
Bluetooth 3.0, 2.0 or 1.2 systems.
It incorporates Bluetooth 1M/2M/3Mbps
RF, single-cycle MCU, MODEM, UART
interface, and ISSC’s own Bluetooth software
stack to achieve the required BT v4.1 with
EDR functions.
To provide the superior audio and voice
quality, it also integrates a DSP co-processor, a
PLL, and a CODEC dedicated for voice and
audio applications.
For voice, not only basic CVSD encoding
and decoding but also enhanced noise
reduction and echo cancellation are
implemented by the built-in DSP to reach the
better quality in the both sending and receiving
sides. For enhanced audio applications, SBC
and AAC (optional) decoding functions can be
also carried out by DSP to satisfy Bluetooth
A2DP requirements.
In addition, to minimize the external
components required for portable devices, a
build-in class-D amplifier for audio output, a
voltage sensor for battery, battery charger and
LDO are integrated to reduce BOM cost for
various Bluetooth applications.
FEATURES
Support preliminary Bluetooth v4.1
function and backward compatible with
BT3.0, 2.0 and 1.2.
ISSC’s own Bluetooth software stack for
the headset or speaker application. It
supports following profiles :
- Hands Free 1.6
- Headset 1.1
- A2DP 1.2
- AVRCP 1.5
- SPP 1.0
Integrated 16/32 bits DSP core running up
to 72MHz that supports:
- Noise suppression
- Echo suppression
- SBC/AAC (optional) audio format
decoding
- Automatic volume control for mono
speaker output
Integrated a 20-bit 98dB SNR
( A-weighted) audio DAC
Connections to two phones with
HFP/A2DP profiles
Built-in four languages ( Chinese/
English/ Spanish/ French) voice prompts
Build-in a 2W class-D amplifier for audio
output
Capable charging voltage from an empty
battery and sustain a direct DC input
voltage up to 7V
Charging current up to 350mA
7 mm x 7 mm QFN 56 package
APPLICATIONS
Bluetooth mono speaker
Bluetooth mono speaker phone
Bluetooth mono car audio unit
Phone: 886-3-577-8385
Website: www,issc-tech.com
Draft 0.9 Mar 12, 2014.
1 page  
APPLICATION DIAGRAM
Data Sheet
IS2015S
-5-
5 Page 
Data Sheet
IS2015S
4 MICROPROCESSOR
A single-cycle 8-bit MCU is inside IS2015S to carry out the required Bluetooth protocols. It
can run at the range from 16MHz to a higher clock so that MCU firmware can dynamically
consider the tradeoff between computing power and power consumption. MCU firmware is
implemented in ROM (Read-Only-Memory) to minimize the power consumption of program
execution and to save the cost of external flash.
MEMORY
A single-port synchronous interface is provided to memory. There are enough ROM and
RAM to fulfill the requirement of processor. In addition, attached to the embedded processor bus
are a register bank, a dedicated single-port memory, and flash memory. The processor coordinates
all link control procedures and data movement using a set of pointer registers.
EXTERNAL RESET
A watchdog timer capable of reset the chip. It has an integrated Power-On Reset (POR)
circuit that resets all circuits to a known power-on state. This action can also be driven by an
external reset signal that can be used to externally control the device, forcing it into a power-on
reset state. The RST signal input is active low and no connection is required in most applications.
REFERENCE CLOCK
IS2015S is composed of an integrated crystal oscillation function. It used a 16 MHz external
crystal and two specified load capacitors that a high quality system reference timer source is
obtained. This feature is typically used to remove the initial tolerance frequency errors associated
with the crystal and its equivalent load capacitance in mass production. Frequency trim is achieved
by adjusting the crystal load capacitance through on-chip trim capacitors Ctrim integrated in chip.
The value of trimming capacitance is around 200fF per LSB at 5 bits word, therefore the
overall adjustable clock frequency is around 40 KHz.
Ctrim =200fF * (1~31)
- 11 -
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet IS2015S.PDF ] | |
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