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PDF 74LVC04A Data sheet ( Hoja de datos )
| Número de pieza | 74LVC04A | |
| Descripción | Hex inverter | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74LVC04A
Hex inverter
Rev. 9 — 17 November 2011
Product data sheet
1. General description
The 74LVC04A provides six inverting buffers. Inputs can be driven from either 3.3 V or 5 V
devices. This feature allows the use of these devices as translators in mixed 3.3 V
and 5 V applications.
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74LVC04AD 40 C to +125 C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74LVC04ADB 40 C to +125 C SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
74LVC04APW 40 C to +125 C TSSOP14 plastic thin shrink outline package; 14 leads;
body width 4.4 mm
74LVC04ABQ 40 C to +125 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1
1 page  
NXP Semiconductors
74LVC04A
Hex inverter
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
40 C to +85 C
Min Typ[1] Max
ICC
ICC
supply
current
additional
supply
current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
per input pin;
VCC = 2.7 V to 3.6 V;
VI = VCC 0.6 V; IO = 0 A
-
-
0.1 10
5 500
CI input
VCC = 0 V to 3.6 V;
capacitance VI = GND to VCC
- 4.0 -
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
10. Dynamic characteristics
40 C to +125 C
Min Max
- 40
Unit
A
-
5 000
A
- - pF
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
Conditions
40 C to +85 C
Min Typ[1] Max
tpd propagation delay nA to nY; see Figure 6
[2]
VCC = 1.2 V
- 14 -
VCC = 1.65 V to 1.95 V
0.3 3.7 8.8
VCC = 2.3 V to 2.7 V
0.5 2.2 5.0
VCC = 2.7 V
1.0 2.1 5.5
tsk(o)
CPD
output skew time
power dissipation
capacitance
VCC = 3.0 V to 3.6 V
VCC = 3.0 V to 3.6 V
per buffer; VI = GND to VCC
VCC = 1.65 V to 1.95 V
1.0 2.0 4.5
[3] -
- 1.0
[4]
- 3.9 -
VCC = 2.3 V to 2.7 V
- 7.1 -
VCC = 3.0 V to 3.6 V
- 9.9 -
40 C to +125 C Unit
Min Max
- - ns
0.3 10.2 ns
0.5 5.8 ns
1.0 7.0 ns
1.0 6.0 ns
- 1.5 ns
- - pF
- - pF
- - pF
[1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs
11. Waveforms
74LVC04A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 17 November 2011
© NXP B.V. 2011. All rights reserved.
5 of 15
5 Page 
NXP Semiconductors
74LVC04A
Hex inverter
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
D BA
terminal 1
index area
A
A1
E
c
detail X
terminal 1
index area
L
e
2
1
Eh
14
e1
b
6
vM C AB
wM C
7
e
8
y1 C
C
y
13 9
Dh
0 2.5
5 mm
X
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c D(1) Dh E(1) Eh e e1 L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1 1.65
2.9 1.35
2.6
2.4
1.15
0.85
0.5
2
0.5
0.3
0.1 0.05 0.05 0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
EUROPEAN
PROJECTION
SOT762-1
---
MO-241
---
ISSUE DATE
02-10-17
03-01-27
Fig 11. Package outline SOT762-1 (DHVQFN14)
74LVC04A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 17 November 2011
© NXP B.V. 2011. All rights reserved.
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