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PDF RNA51A26FLPEL Data sheet ( Hoja de datos )
| Número de pieza | RNA51A26FLPEL | |
| Descripción | CMOS system-RESET IC | |
| Fabricantes | Renesas | |
| Logotipo |  |
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Data Sheet
RNA51xx Series
CMOS system–RESET IC
R03DS0090EJ0400
Rev.4.00
Jan 10, 2014
General Description
The RNA51xx series provide system reset signal for microprocessor and electrical systems.
Threshold voltage is 1.4 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.4 V, 4.5 V, 4.6 V, 5.0 V and accuracy is ±1.0%.
The reset output delay time can be set by external capacitor connected to CD pin.
Manual reset input is available and input resistance is 2 MΩ typ.
This series have two output types (active-low CMOS output and active-low open-drain output).
Features
• Threshold voltage: 1.4 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.4 V, 4.5 V, 4.6 V, 5.0 V
• Threshold voltage accuracy: ±1.0%
• Threshold voltage hysteresis: 5% typ.
• Low supply current: 0.7 μA typ.
• Capacitor-adjustable output delay time
• Manual reset
• VOUT CMOS output, or open-drain output
• 5-pin SOT-23 package
• Temperature range: –40°C to 85°C
• Ordering Information
Part Name
RNA51A26FLPEL
RNA51A27FLPEL
RNA51A28FLPEL
RNA51A29FLPEL
RNA51A30FLPEL
RNA51A31FLPEL
RNA51A44FLPEL
RNA51A45FLPEL
RNA51A46FLPEL
RNA51B14FLPEL
RNA51B27FLPEL
RNA51B50FLPEL
Package Type
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
Package Code
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
Package
Abbreviation
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
Taping Abbreviation
(Quantity)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
Applications
• Power supply voltage monitoring for microprocessors
• Battery-powered portable equipment
• Computers and notebook computers
• Wireless Communication Systems
• Digital still camera, digital video camera, PDA
R03DS0090EJ0400 Rev.4.00
Jan 10, 2014
Page 1 of 11
1 page  
RNA51xx Series
Electrical characteristics
(1) RNA51Axx Products
Item
Supply voltage
Supply current
Threshold voltage
Temperature coefficiency of the
thereshold voltage
(Reference value)
Threshold voltage hysteresis
VOUT low-level output current
VOUT Output leakage current
(open drain output)
Delay time Note1
MR Low-level input voltage Note2
MR High-level input voltage
MR internal pull-up resistance
Symbol
VDD
Min
1.1
IDD
–VTH
Δ(–VTH)
–VTH ⋅ΔTa
⎯
–VTH×0.99
⎯
Typ
⎯
0.7
⎯
±100
Max
5.5
4.2
–VTH×1.01
⎯
Temperature condition Ta = 25°C
Unit Conditions
V pull-up resistor = 470 kΩ
VOUT ≤ 0.1×VDD
μA VDD = 5.5 V
V
ppm/ Ta = –40 to 85°C
°C
VHYS
IOL
ILEAK
–VTH×3%
0.2
3.4
⎯
–VTH×5%
1.2
7.0
⎯
–VTH×8%
⎯
⎯
0.1
V
mA VOUT = 0.5 V
VDD = 1.3 V
VDD = 2.4 V
(–VTH ≥ 2.7 V)
μA VDD = VOUT = 5.5 V
tDLY 10 20 35 ms VDD = 1.1 to 5.5V, tTLH = 1 μs
CD = 4.7 nF
VIL
⎯
⎯
VDD×0.25
V
VIH VDD×0.75 ⎯
⎯V
RMR
1
2
7 MΩ
(2) RNA51Bxx Products
Temperature condition Ta = 25°C
Item
Symbol
Min
Typ
Max
Unit
Conditions
Supply voltage
Supply current
VDD 1.1 ⎯ 5.5 V pull-up resistor = 470 kΩ
VOUT ≤ 0.1×VDD
IDD ⎯ 0.7 4.2 μA VDD = 5.5 V
Threshold voltage
Threshold voltage
temperature dependency
(Reference value for design)
Threshold voltage hysteresis
VOUT low-level output current
VOUT High-level output current
(CMOS output)
Delay time Note1
MR Low-level input voltage Note2
MR High-level input voltage
MR internal pull-up resistance
–VTH
Δ(–VTH)
–VTH ⋅ΔTa
–VTH×0.99
⎯
⎯
±100
–VTH×1.01
⎯
V
ppm/
°C
Ta = –40 to 85°C
VHYS
IOL
IOH
tDLY
VIL
VIH
RMR
–VTH×3%
0.2
3.4
–1.4
–1.5
10
⎯
VDD×0.75
1
–VTH×5%
1.2
7.0
–2.7
–3.0
20
⎯
⎯
2
–VTH×8%
⎯
⎯
⎯
⎯
35
VDD×0.25
⎯
7
V
mA VOUT = 0.5 V
VDD = 1.3 V
VDD = 2.4 V
(–VTH ≥ 2.7 V)
mA VOUT =
VDD–0.5 V
VDD = 4.5 V
(–VTH ≤ 4.0 V)
VDD = 5.5 V
ms VDD = 1.1 to 5.5 V, tTLH = 1 μs
CD = 4.7 nF
V
V
MΩ
Note: 1. Delay time is specified when charging starts in the condition that CD pin is completely discharged. When discharging of CD
pin is not complete because of immediate stop and other reasons, the delay time is not guaranteed. Therefore, when
passing of VDD pin input voltage immediately stops (the period of condition that VDD pin input voltage is lower than the
detected voltage is short), discharging of external capacitor CD is inadequate, and the delay time becomes much shorter
than the minimum guaranteed value. Be sure to fully check that there are no problems as the system.
2. Minimum value of low-pulse width to be input to MR pin depends on the value of external capacitor CD. Therefore, set the
low-pulse width to be input to MR pin to the minimum input low-pulse width shown in figure 1 or more.
R03DS0090EJ0400 Rev.4.00
Jan 10, 2014
Page 5 of 11
5 Page 
RNA51xx Series
Package Dimensions
JEITA Package Code
SC-74A
RENESAS Code
PLSP0005ZB-A
Previous Code
MPAK-5 / MPAK-5V
MASS (Typ) [g]
0.015
D
e
A
Qc
E HE
AA
xM S A
b
L
L1
A3
LP
yS
b
c
A-A Section
A2 A
A1
S
Reference Dimensions in millimeters
Symbol Min Nom Max
A 1.0 ⎯ 1.4
A1 0 ⎯ 0.1
A2 1.0 1.1 1.3
A3 ⎯ 0.25 ⎯
b 0.35 0.4 0.5
c 0.11 0.16 0.26
D 2.8 2.95 3.1
E 1.5 1.6 1.8
e ⎯ 0.95 ⎯
HE 2.5 2.8 3.0
L 0.3 ⎯ 0.7
L1 0.1 ⎯ 0.5
LP 0.2 ⎯ 0.6
x ⎯ ⎯ 0.05
y ⎯ ⎯ 0.05
Q ⎯ 0.3 ⎯
© 2013 Renesas Electronics Corporation. All rights reserved.
R03DS0090EJ0400 Rev.4.00
Jan 10, 2014
Page 11 of 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet RNA51A26FLPEL.PDF ] | |
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