|
|
PDF PI6LC48P21 Data sheet ( Hoja de datos )
| Número de pieza | PI6LC48P21 | |
| Descripción | Single Output LVPECL Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PI6LC48P21 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
|
No Preview Available !
PI6LC48P21
Single Output LVPECL Clock Generator
Features
ÎÎSingle differential LVPECL output
ÎÎSupports the following output frequencies: 125MHz or
133MHz
ÎÎRMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.3ps (typical)
ÎÎFull 3.3V or 2.5V supply modes
ÎÎCommercial and industrial ambient operating temperature
ÎÎAvailable in lead-free package: 8-TSSOP
Description
The PI6LC48P21 is a single output LVPECL synthesizer opti-
mized to generate Ethernet reference clock frequencies and is a
member of Pericom’s HiFlex family of high performance clock
solutions. Using a 25MHz or 26.6MHz crystal, it can generate
125MHz or 133MHz output frequencies.
The PI6LC48P21 uses Pericom’s proprietary low phase noise
PLL technology to achieve ultra low phase jitter, so it is ideal for
Ethernet interface in all kind of systems.
Applications
ÎÎNetworking systems
Block Diagram
XTAL_IN
XTAL_OUT
OSC
PFD VCO
/25
/5
Pin Configuration
VDDA 1
CLK
CLK#
GND 2
XTAL_OUT 3
XTAL_IN 4
8 VDD
7 CLK
6 CLK#
5 NC
13-0096
1 www.pericom.com
PI6LC48P21
Rev. A
06/19/13
1 page  
LVPECL Test Circuit
Device
150Ω
150Ω
ZO = 50Ω
L = 0 ~ 10in
ZO = 50Ω
PI6LC48P21
Single Output LVPECL Clock Generator
0.01µF
50Ω
0.01µF
50Ω
Power Supply Filtering Techniques
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The PI6LC48P21 provides separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and
0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the VDDA pin.
VDD
3.3V or 2.5V
0.1µF
10Ω *
VDDA
0.1µF
10µF
* If VDD is 2.5V, the resistor value will be di erent, see app note for details
13-0096
5 www.pericom.com
PI6LC48P21
Rev. A
06/19/13
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PI6LC48P21.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PI6LC48P21 | Single Output LVPECL Clock Generator | Pericom Semiconductor |
| PI6LC48P25104 | Single Output LVPECL Clock Generator | Pericom Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |