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PDF PI6LC48P0301A Data sheet ( Hoja de datos )
| Número de pieza | PI6LC48P0301A | |
| Descripción | 3-Output LVPECL Networking Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
Features
ÎÎThree differential LVPECL output pairs
ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL
single-ended clock input
ÎÎSupports the following output frequencies: 125MHz,
156.25MHz, 312.5MHz, 625MHz
ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.26ps (typical)
ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.4ps (max)
ÎÎFull 3.3V or 2.5V supply modes
ÎÎCommercial and industrial ambient operating temperature
ÎÎAvailable in lead-free package: 28-TQFN
Description
The PI6LC48P0301A is a 3-output LVPECL synthesizer opti-
mized to generate Ethernet reference clock frequencies and is
a member of Pericom’s HiFlexTM family of high performance
clock solutions. Using a 25MHz or other fundamental frequency
crystal, the most popular Ethernet frequencies can be generated
based on the settings of 4 frequency select pins.
The PI6LC48P0301A uses Pericom’s proprietary low phase noise
PLL technology to achieve ultra low phase jitter, so it is ideal for
Ethernet interface in all kind of systems.
Applications
ÎÎNetworking systems
Block Diagram
XTAL_IN
XTAL_OUT
Ref_IN
IN_SEL#
FBN
M_reset
OSC
PFD VCO
NA_SEL[0:1]
/A
/B
M
PLL_ByPass#
NB_SEL[0:1]
OEA
OEB
CLKA
CLKA#
CLKB0
CLKB0#
CLKB1
CLKB1#
14-0083
1 www.pericom.com PI6LC48P0301A
Rev. A
06/03/2014
1 page  
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
Maximum Ratings (Over operating free-air temperature range)
Note:
Storage Temperature............................................... -65ºC to+155ºC
Ambient Temperature with Power Applied..........-40ºC to+85ºC
3.3V Analog Supply Voltage.......................................-0.5 to +3.6V
ESD Protection (HBM).......................................................... 2000V
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics
Power Supply DC Characterisitcs, (TA = -40 to 85ºC)
Symbol Parameter
Condition
Min Typ Max Units
VDD
VDDA
VDDO_A
VDDO_B
VDD
VDDA
VDDO_A
VDDO_B
IGND
IDDA
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135 3.3 3.465
3.135 3.3 3.465
V
V
3.135 3.3 3.465
V
2.375 2.5 2.625
2.375 2.5 2.625
V
V
2.375 2.5 2.625
V
150 mA
37 mA
LVCMOS/LVTTL DC Characterisitcs, (TA = -40 to 85ºC)
Symbol Parameter
Condition
VIH Input High Voltage
VIL Input Low Voltage
VDD = 3.3 V +/- 5%
VDD = 2.5 V +/- 5%
VDD = 3.3 V +/- 5%
VDD = 2.5 V +/- 5%
Ref_IN, FBN, M_reset
VDD = VIN = 3.465V
IIH Input High Current OEA, OEB, PLL_By-
pass#, IN_SEL#, NA_
SEL[1:0], NB_SEL[1:0]
VDD = VIN = 3.465V
Ref_IN, FBN, M_reset
VDVD I=N
3.465V,
= 0V
IIL
Input Low Current
OEA, OEB, PLL_By-
pass#, IN_SEL#, NA_
SEL[1:0], NB_SEL[1:0]
VDVD I=N
3.465V,
= 0V
Min
2
1.7
-0.3
-0.3
-5
-150
Typ Max Units
VDD+ 0.3
VDD+ 0.3
0.8
V
V
0.7 V
150 µA
5 µA
µA
µA
14-0083
5 www.pericom.com PI6LC48P0301A
Rev. A
06/03/2014
5 Page 
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram
is shown in the figure below. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS
signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with
the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resis-
tance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in
half. This can be done in one of the two ways. First, R1 and R2 in parallel should equal the transmission line empedance. For most
50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the
crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal.
VDD
Ro
Rs
Zo = Ro + Rs
50Ω
VDD
R1
0.1µF
XTAL_IN
R2
XTAL_OUT
Thermal Information
Symbol
QJA
QJC
Description
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
Condition
Still air
41.68 OC/W
23.78 OC/W
14-0083
11 www.pericom.com PI6LC48P0301A
Rev. A
06/03/2014
11 Page | ||
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| PDF Descargar | [ Datasheet PI6LC48P0301A.PDF ] | |
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