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PDF PI6LC48P03 Data sheet ( Hoja de datos )
| Número de pieza | PI6LC48P03 | |
| Descripción | 3-Output LVPECL Networking Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6LC48P03
3-Output LVPECL Networking Clock Generator
Features
ÎÎThree differential LVPECL output pairs
ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL
single-ended clock input
ÎÎSupports the following output frequencies: 125MHz,
156.25MHz, 312.5MHz, 625MHz
ÎÎRMS phase jitter @ 156.25MHz, using a 31.25MHz or
26.041666MHz crystal (12kHz – 20MHz): 0.3ps (typical)
ÎÎFull 3.3V or 2.5V supply modes
ÎÎCommercial and industrial ambient operating temperature
ÎÎAvailable in lead-free package: 24-TSSOP
Description
The PI6LC48P03 is a 3-output LVPECL synthesizer optimized to
generate Ethernet reference clock frequencies and is a member
of Pericom’s HiFlex family of high performance clock solutions.
Using a 31.25MHz or 26.041666MHz crystal, the most popular
Ethernet frequencies can be generated based on the settings of 4
frequency select pins.
The PI6LC48P03 uses Pericom’s proprietary low phase noise
PLL technology to achieve ultra low phase jitter, so it is ideal for
Ethernet interface in all kind of systems.
Applications
ÎÎNetworking systems
Block Diagram
XTAL_IN
XTAL_OUT
Ref_IN
IN_SEL#
FBN
M_reset
OSC
PFD VCO
NA_SEL[0:1]
/A
/B
M
PLL_ByPass#
NB_SEL[0:1]
OEA
OEB
CLKA
CLKA#
CLKB0
CLKB0#
CLKB1
CLKB1#
15-0059
1 www.pericom.com
PI6LC48P03
Rev. C
5/7/2015
1 page  
PI6LC48P03
3-Output LVPECL Networking Clock Generator
LVPECL DC Characterisitcs, (TA = -40 to 85ºC)
Symbol Parameter
Condition
VOH Output High Voltage(1)
VDD = 3.3V
VDD = 2.5V
VOL Output Low Voltage(1)
VDD = 3.3V
VDD = 2.5V
Note: 1. LVPECL Termination: Source 150ohm to GND and 100ohm across CLK and CLK#.
Min Typ Max Units
1.9
1.1
2.4
1.6
V
1.2
0.4
1.6
0.8
V
AC Electrical Characteristics (TA = -40 to 85ºC)
LVPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND
Symbol Parameter
fOUT
tsk(B)
tsk(o)
Output Frequency
Output Skew(1)
Output Skew(2,4)
tjit(Ø)
RMS Phase Jitter,
(Random)(3)
tR / tF
oDC
Output Rise/Fall Time
Output Duty Cycle (5)
Condition
NA_SEL[1:0] / NB_SEL[1:0] = 00
NA_SEL[1:0] / NB_SEL[1:0] = 01
NA_SEL[1:0] / NB_SEL[1:0] = 10
NA_SEL[1:0] / NB_SEL[1:0] = 11
Output with same VDD and load
Output @ Same Frequencies
Output @ Different Frequencies
625MHz,
(1.875MHz - 20MHz)
625MHz,
(12kHz - 20MHz)
312.5MHz,
(1.875MHz - 20MHz)
312.5MHz,
(12kHz - 20MHz)
156.25MHz,
(1.875MHz - 20MHz)
156.25MHz,
(12kHz - 20MHz)
125MHz, Freq Select 110,
(1.875MHz - 20MHz)
125MHz, Freq Select 110,
(12kHz - 20MHz)
20% to 80%
Min.
560
280
140
112
48
Typ.
0.15
0.3
0.15
0.3
0.15
0.3
0.15
0.3
Max
700
350
175
140
30
120
150
400
52
Note:
1. Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
2. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
3. Please refer to the Phase Noise Plots.
4. This parameter is defined in accordance with JEDEC Standard 65. Measured at the differential cross points.
5. Measured at the differential cross points.
15-0059
5 www.pericom.com
PI6LC48P03
Rev. C
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
5/7/2015
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet PI6LC48P03.PDF ] | |
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