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PDF PI6LC48P0201 Data sheet ( Hoja de datos )
| Número de pieza | PI6LC48P0201 | |
| Descripción | 2-Output LVPECL Networking Clock Generator | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6LC48P0201
2-Output LVPECL Networking Clock Generator
Features
ÎÎTwo differential LVPECL output pairs
ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL
single-ended clock input
ÎÎSupports the following output frequencies: 62.5MHz,
125MHz, 156.25MHz
ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.14ps (typical)
ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.3ps (typical)
ÎÎFull 3.3V or 2.5V supply modes
ÎÎIndustrial operating temperature
ÎÎAvailable in lead-free package: 20-TSSOP
Description
The PI6LC48P0201 is a 2-output LVPECL synthesizer opti-
mized to generate Ethernet reference clock frequencies and is a
member of Pericom’s HiFlex family of high performance clock
solutions. Using a 25MHz crystal, the most popular Ethernet
frequencies can be generated based on the settings of 2 frequen-
cy select pins.
The PI6LC48P0201 uses Pericom’s proprietary low phase noise
PLL technology to achieve ultra low phase jitter, so it is ideal for
Ethernet interface in all kind of systems.
Applications
ÎÎNetworking systems
Block Diagram
XTAL_IN
XTAL_OUT
Ref_IN
IN_SEL
OSC
M_reset
PFD VCO
M
PLL_ByPass
N_SEL[0:1]
/N
CLK0
CLK0#
CLK1
CLK1#
15-0107
1 www.pericom.com
PI6LC48P0201
Rev. D
08/05/15
1 page  
PI6LC48P0201
2-Output LVPECL Networking Clock Generator
LVPECL DC Characterisitcs, (TA = -40ºC to 85ºC)
Symbol Parameter
Condition
VOH Output High Voltage(1)
VDD = 3.3V
VDD = 2.5V
VOL Output Low Voltage(1)
VDD = 3.3V
VDD = 2.5V
Note: 1. LVPECL Termination: Source 150ohm to GND and 100ohm across CLK and CLK#.
Min Typ Max Units
1.9
1.1
2.4
1.6
V
1.2
0.4
1.6
0.8
V
AC Electrical Characteristics, (TA = -40ºC to 85ºC)
LVPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND
Symbol Parameter
Condition
Min. Typ. Max
fOUT Output Frequency
N_SEL[1:0] = 00
N_SEL[1:0] = 01, 11
N_SEL[1:0] = 10
140
112
56
170
136
68
tsk(o)
Output Skew(1, 3)
tjit(Ø)
RMS Phase Jitter,
(Random)(2)
Outputs with the same loading
156.25MHz,
(1.875MHz - 20MHz)
156.25MHz,
(12kHz - 20MHz)
125MHz,
(1.875MHz - 20MHz)
125MHz,
(12kHz - 20MHz)
62.5MHz,
(1.875MHz - 20MHz)
62.5MHz,
(12kHz - 20MHz)
70
0.14
0.3
0.13
0.28
0.25
0.36
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
400
48 52
Note:
1. Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
2. Please refer to the Phase Noise Plots.
3. This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
%
15-0107
5 www.pericom.com
PI6LC48P0201
Rev. D
08/05/15
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet PI6LC48P0201.PDF ] | |
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